1
Note: This is a summary document. A complete document is not available
at this time. For more information, please contact your local Atmel sales
office.
5344AS–BDC–09/03
Main Features
Programmable DMUX Ratio:
– 1:4 Data Rate Max = 1 Gsps
– P
D
(8b/10b) < 4.3/4.7 W (ECL 50
Output)
– 1:8 Data Rate Max = 2 Gsps
– P
D
(8b/10b) < 6/6.9 W (ECL 50
Output)
– 1:16 With 1 TS8388B or 1 TS83102G0 and 2 DMUX
Parallel Output Mode
8/10-bit
ECL Differential Input Data
Data Ready or Data Ready 2 Input Clock
Input Clock Sampling Delay Adjust
Single-ended Output Data:
– Adjustable Common Mode and Swing
– Logic Threshold Reference Output
– ECL, PECL, TTL
Asynchronous Reset
Synchronous Reset
ADC and DMUX Multi-channel Applications:
– Stand-alone Delay Adjust Cell for ADCs Sampling Instant Alignment
Differential Data Ready Output
Built-in Self Test (BIST)
Dual Power Supply V
EE
= -5 V, V
CC
= 5 V
Radiation Tolerance Oriented Design (More Than 100 Krad (Si) Expected)
Thermally Enhanced CQFP196 Cavity Up Package
Screening
Temperature Range:
–
C Grade: 0°C < Tc; Tj < 90°C
–
V Grade: -40°C < Tc; Tj < 110°C
–
M Grade: -55°C < Tc; Tj < 125°C
Standard Screening Level for “C”, “V” and “M” Grades
ESA SCC 9000 Space Screening Flow for “M” Grade (on Request)
Note:
For commercial and industrial temperature ranges the DMUX is also available in a
TBGA240 package (P/N: TS81102G0CTP and TS81102G0VTP).
Description
The TS81102G0 is a monolithic 10-bit high-speed (up to 2 Gsps) demultiplexer.
The DMUX is designed to run with all kinds of ADCs and more specifically, it fits per-
fectly with Atmel’s high-speed ADC 8-bit 1 Gsps TS8388B and ADC 10-bit 2 Gsps
TS83102G0B. The TS81102G0 uses an innovative architecture, including a sampling
delay adjust and tunable output levels. This DMUX allows users to process the high-
speed output data stream down to standard signal processors speed (standard
FPGAs).
1:4/1:8 8/10-bit
2 Gsps
DMUX
TS81102G0FS
Target
Specification
Summary
For more information please
contact
hotline-bdc@gfo.atmel.com