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參數(shù)資料
| 型號： | TS68EN360VR25L |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-bit Quad Integrated Communication Controller |
| 中文描述： | 32-BIT, 25 MHz, RISC PROCESSOR, CPGA241 |
| 封裝： | CERAMIC, PGA-241 |
| 文件頁數(shù)： | 74/82頁 |
| 文件大?。?/td> | 874K |
| 代理商： | TS68EN360VR25L |
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74
TS68EN360
2113A–HIREL–03/02
TheCPprovidesthecommunicationfeaturesoftheQUICC.IncludedareaRISCpro-
cessor,fourSCCs,twoSMCs,oneSPI,2.5Kbytesofdual-portRAM,aninterrupt
controller,atimeslotassigner,threeparallelports,aparallelinterfaceport,fourinde-
pendentbaudrategenerators,andfourteenserialDMAchannelstosupporttheSCCs,
SMCs,andSPI.
TheIDMAsprovidetwochannelsofgeneral-purposeDMAcapability.Theyofferhigh-
speedtransfers,32-bitdatamovement,bufferchaining,andindependentrequestand
acknowledgelogic.TheRISCcontrollermayaccesstheIDMAregistersdirectlyinthe
bufferchainingmodes.TheQUICCIDMAsaresimilarto,yetenhancementsof,theone
IDMAchannelfoundontheTS68302.
Thefourgeneral-purposetimersontheQUICCarefunctionallysimilartothetwogen-
eral-purposetimersfoundontheTS68302.However,theyoffersomeminor
enhancements,suchastheinternalcascadingoftwotimerstoforma32-bittimer.The
QUICCalsocontainsaperiodicintervaltimerintheSIM60,bringingthetotaltofive
on-chiptimers.
EthernetonQUICC
TheEthernetprotocolisavailableonlyontheEthernetversionoftheQUICCcalledthe
TS68EN360.Thenon-EthernetversionoftheQUICCistheMC68360.Theterm
“QUICC”istheoveralldevicenamethatdenotesallversionsofthedevice.
TheTS68EN360isasupersetoftheMC68360,havingtheadditionaloptionallowing
EthernetoperationonanyofthefourSCCs.DuetoperformancereasonnotassSCCs
canbeconfiguredasEthernetcontrolleratthesametime.TheTS68EN360isnot
restrictedonlytoEthernetoperation.HDLC,UART,andotherprotocolsmaybeusedto
allowdynamicswitchingbetweenprotocols.SeeAppendixASerialPerformancefor
availableSCCperformance.
WhentheMODEbitsoftheSCCGSMRselecttheEthernetprotocol,thenthatSCC
performsthefullsetofIEEE802.3/EthernetCSMA/CDmediaaccesscontrolandchan-
nelinterfacefunctions(seeFigure73).
Figure73.
EthernetBlockDiagram
IMB
CONTROL
REGISTERS
SLOT TIME
AND DEFER
COUNTER
CLOCK
GENERATOR
PERIPHERAL BUS
RECEIVER
CONTROL
UNIT
RECEIVE
DATA
FIFO
TRANSMITTER
CONTROL
UNIT
TRANSMIT
DATA
FIFO
SHIFTER
SHIFTER
TXD
RXD
RRJCT
RSTRT
CD = RENA
CTS = CLSN
CD = RENA
CTS = CLSN
RTS = TENA
INTERNAL CLOCKS
RX CLOCK
TX CLOCK
R
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