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參數(shù)資料
| 型號(hào)： | TS68C429AMR |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CMOS ARINC 429 Multichannel Receiver/ Transmitter MRT |
| 中文描述： | 3 CHANNEL(S), 2.5M bps, SERIAL COMM CONTROLLER, CPGA84 |
| 封裝： | PGA-84 |
| 文件頁數(shù)： | 18/43頁 |
| 文件大?。?/td> | 1638K |
| 代理商： | TS68C429AMR |
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18
TS68C429A
2120A–HIREL–08/02
The lowest value will give the highest priority. If two channels have the same priority,
one of them will never be able to send its interrupt vector to the microprocessor. Each
channel must have a unique channel priority order.
Figure 11.
15 14 13 12 11 10 9
8
7
6 5
4
3
2
1
0
Channel enable
Test mode
Label control
Label control matrix write enable
Parity control
Not used
Wrong parity
Not used
Channel priority order
USD access
LDS access
Table 9.
Register Control Register Description
Bit
Function
Comments
Bit 15
Channel enable
0: channel is out of service
1: channel is in service
Bit 14
Test mode
0: external ARINC lines as input (normal operation)
1: third transmitter lines as input (test mode)
Bit 13
Label control
0: no control, all the labels are accepted
1: automatic check of the label according to the label control matrix
Bit 12
LCMWE label control matrix
write enable
0: receiving mode (write to the matrix are disabled)
1: programmation mode for labels control matrix
Bit 11
Parity control
0: even parity check
1: odd parity check
Bit 10
Parity control
0: parity check is disable
1: parity check is enable
Bit 9
Not used
Bit 8
Not used
Bit 7
Wrong parity: this feature is
enabled only if the self-test
register bit 0 is set 1
0: received message parity is correct if read, reset wrong wrong parity flag if written.
1: an incorrect received message parity has been detected (the corresponding
message is lost) (set by hardware).
Bit 6
Not used
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