參數(shù)資料
型號(hào)： TS68C429ADESCxx
廠(chǎng)商： Atmel Corp.
英文描述： CMOS ARINC 429 Multichannel Receiver/ Transmitter MRT
中文描述： ARINC公司429多通道的CMOS接收器/發(fā)送捷運(yùn)
文件頁(yè)數(shù)： 19/43頁(yè)
文件大?。?/td> 1638K
代理商： TS68C429ADESCXX
19
TS68C429A
2120A–HIREL–08/02
Gap Register (Figure 12)
The gap register is accessible for writing operations only. It contains the value on which
the gap counter will be stopped and will generate the end of the message signal (see
“Inputs” on page 14). The value is interpreted as a multiple of the CLK ARINC period.
Figure 12.
Gap Register Description
The value of the gap register must be chosen so as to generate the end of the message
before the minimal gap as defined in the ARINC-429 norm.
Message Buffer
The Buffer is made of two 16-bit registers, the Most Significant Word of the message
(MSW) is contained in the lower address register, the Least Significant Word of the mes-
sage (LSW) is contained in the upper address register. For correct behavior, the MSW
must be read before the LSW. They are accessible in read mode only and 16-bit access
is mandatory.
Label Control Matrix
The label control matrix is a 256 x 1 bit memory. There is one memory per channel.
The address is driven by the incoming label, the output data is used to validate this
incoming message label (see Figure 13). To program this matrix, the LCMWE (label
control matrix write enable) bit of the receiver-control-register should be set to “1” to
allow the access. At this time, the address is driven by the external address bus and the
data are written from the data bus D7 to D0 (one per channel according to Figure 14).
Any write to a matrix on which the LCMWE is not set will not have any effect. The label
control matrix can be written or read in byte and word mode. In word mode, the state of
D15-D8 is unknown. After complete programming of the matrix, the LCMWE bit should
be reset to “0” to allow normal receiving mode. A “1” in the memory means that this label
is allowed and a “0” means that this label must be ignored.
Bit 5
Not used
Bit 4
Not used
Bit 0 to 3
Channel priority: order
The lowest value will give the highest priority. Each channel must have a unique
channel priority order.
If several messages are pending, the interrupt vector will account for highest priority
channel.
Table 9.
Register Control Register Description
Bit
Function
Comments
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參數(shù)描述
TS68C429AMF 功能描述:IC MULTI-CH CTRLR 132CQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類(lèi)型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱(chēng):Q6396337A
TS68C429AMF1B/C 制造商:ATMEL 制造商全稱(chēng):ATMEL Corporation 功能描述:CMOS ARINC 429 Multichannel Receiver/ Transmitter MRT
TS68C429AMF1BC 制造商:e2v technologies 功能描述:TS68C429AMF1BC - Trays
TS68C429AMF1BCA 制造商:e2v technologies 功能描述:TS68C429AMF1BCA - Trays
TS68C429AMFA 制造商:e2v technologies 功能描述:MULTI CH RCVR/TRANSMITTER 132CQFP - Trays
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