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參數(shù)資料
| 型號： | TRU2500-C |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 825K |
| 代理商： | TRU2500-C |
Vectron International 166 Glover Avenue, Norwalk, CT 06856 Tel: 1-88-VECTRON-1 Fax: 1-888-FAX-VECTRON
P
The TRU-2500 is designed for optimum performance
with a -5 Volt supply. Good high speed grounding and
layout practice should be employed to assure accept-
able performance at this high a data rate. The device
temperature rating is specified as the case tempera-
ture. Consequently good thermal grounding will
increase the useful ambient temperature capability of
the device.
Data inputs are differential with internal AC coupling
to a 50 Ohm termination. This allows a simple inter-
face to a variety of drive circuits, including single
ended inputs.
The TRU2500 design makes use of GaAs HBT tech-
nology to realize lower input offset levels than is
achievable with other FET designs. The extremely low
offset allows the device to operate without bias feed-
back and results in typical input sensitivities as low as
60 mV. Since feedback is not used, it is not necessary
to connect V
TH
to V
FB
. Since V
FB
has no internal
connection, V
TH
and V
FB
may be connected with no ill
effect.
The bias point for each input is accessible through the
V
TH
and V
FB
pins through 1k
V
resistors. Input offset
levels can be adjusted by applying a 0V to -1V bias, to
either or both of the V
FB
and V
TH
pins. This could be
accomplished by individually tying the either or both of
the inputs to -5 V through large variable (100k
V
) resis-
tors. This could be used to optimize the switching
threshold for a particular system or application.
The differential outputs for clock and data are 50
V
CML, as shown in Figure 12. This design has true
50
V
output impedance for optimum reflection coeffi-
cient and reduced sensitivity to variation in intercon-
nect and downstream terminations. The CML output
can interface directly to devices with CML inputs, 50
Ohm to ground, or may be AC coupled to interface
with ECL, PECL.
Vss
DATAOUT DATAOUT
CLKOUT
CLKOUT
LOS
Transition
Detector
Clock
Recovery
Voltage
Reference
1k
1k
50
50
VTH
VFB
NC*
DATAIN
VFB
DATAIN
Vref
C
C
D
D
Programable
Delay
10K
10
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