參數(shù)資料
型號: TRF3750IRGPRG4
廠商: Texas Instruments
文件頁數(shù): 17/37頁
文件大?。?/td> 0K
描述: IC PLL FREQ SYNTHESIZER 20-QFN
標準包裝: 1,000
類型: PLL 頻率合成器
PLL:
輸入: 時鐘
輸出: 時鐘
電路數(shù): 1
比率 - 輸入:輸出: 2:1
差分 - 輸入:輸出: 是/無
頻率 - 最大: 2.4GHz
除法器/乘法器: 是/無
電源電壓: 3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 20-QFN 裸露焊盤(4x4)
包裝: 帶卷 (TR)
配用: TRF3750T-1900EVM-ND - TRF3750T-1900EVM
TRF3750Q1900EVM-ND - TRF3750Q1900EVM
296-20836-ND - EVALUATION MOD FOR CDCM7005-QFN
296-20835-ND - EVALUATION MOD FOR CDCM7005-BGA
296-20834-ND - EVALUATION MOD FOR CDC7005-QFN
TRF3750
SLWS146B MARCH 2004 REVISED AUGUST 2007
www.ti.com
24
Prescaler Selection
DB22DB23 of the function latch controls the prescaler value for the device. There are four possible settings
(9/9, 16/17, 32/33, 64/65). For example, setting (DB23, DB22) = (1,0) results in a prescaler choice of 32/33.
Initialization Latch / Programming After Power Up
Setting (DB1, DB0) = (1,1) selects the initialization latch. The make-up and programming of the initialization
latch is identical to that of the function latch. The difference here is that this latch can be used in order to program
the device at power up. When the initialization latch is programmed, an internal reset occurs at all the counters
(R, A, B) who become ready to get loaded, assuring that the next time data is loaded for the A and B counters
the device begins counting efficiently. Subsequent programming of the A and B counters will not, however,
cause this internal pulse to recur. This pulse is also used to gate the synchronous power down when that mode
is engaged. As soon as the device exits power down, the counting resumes promptly.
Alternate Ways of Programming After Power Up
In addition to the method of using the initialization latch described above, the user can also utilize the CE pin
to achieve initialization. Since the CE does not halt the operation of the serial port, the user can preprogram
the counters and as soon as the device is enabled, the counters operate and the device reaches a steady-state
and functions normally.
A third option in power up is the counter reset method. The function latch is programmed with the desired data,
and in addition DB2 (the counter reset bit) is set to 1. The R counter latch is programmed next, followed by the
N counter latch. Finally, the function latch is programmed again, but this time with a 0 in the bit DB2, disabling
the counter reset. The charge pump is 3-stated during the reset, but the synchronous power down is not
triggered.
Prescaler Resynchronization
DB22 and DB21 of the R counter latch are used to control the delay (DLY) and resynchronization (SYNC)
functions of the device. If SYNC is set to 1, then the output of the prescaler is resynchronized with the RF input.
In addition, if DLY is also 1, the output of the prescaler gets resynchronized with a delayed form of the RF input
signal. In either case, taking the SYNC to 0 reverts the device to normal operation.
The use of the SYNC and DLY functionality can improve the device’s phase noise performance by a few dBs.
It is, however, susceptible to potential malfunction, in case the chosen edge of the RF input coincides with the
prescaler. This phenomenon may be mitigated by using the DLY function, but is nonetheless unpredictable and
care should be applied, as fluctuations in temperature, supply and frequency can alter the point at which the
feature fails to operate. The normal operation of the device calls for both DLY and SYNC to be set to 0, which
is the way the TRF3750 has been characterized.
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