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參數(shù)資料
| 型號(hào)： | TRCV012G5 |
| 廠商： | Lineage Power |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer(2.5 Gbits/s)(限幅放大器，時(shí)鐘恢復(fù)，1：16數(shù)據(jù)多路分解器(2.5 G位/秒)) |
| 中文描述： | 限幅放大器，時(shí)鐘恢復(fù)，1:16數(shù)據(jù)復(fù)用器（2.5 Gb /秒）（限幅放大器，時(shí)鐘恢復(fù)，1:16數(shù)據(jù)多路分解器（2.5摹位/秒）） |
| 文件頁數(shù)： | 5/28頁 |
| 文件大小： | 500K |
| 代理商： | TRCV012G5 |
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Preliminary Data Sheet
August 2000
TRCV012G5 and TRCV012G7
Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
5
Lucent Technologies Inc.
Pin Information
(continued)
Note:
In Table 1, when operating the TRCV012G7 device at the OC-48/STM-16 rate, 2.5 Gbits/s should be inter-
preted as 2.48832 Gbits/s. When operating the TRCV012G7 device at the RS FEC OC-48/STM-16 rate,
2.5 Gbits/s should be interpreted as 2.66606 Gbits/s. (A similar interpretation should be made for 2.5 GHz.)
Table 1. Pin Descriptions—2.5 Gbits/s and Related Signals
* Differential pins are indicated by the P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low.
I = input, O = output. I
u
= an internal pull-up resistor on this pin, I
d
= an internal pull-down resistor on this pin, I
t
= an internal termination
resistance of 50
on this pin.
Pin
30
32
50
51
Symbol
*
LAINP
LAINN
D2G5P
D2G5N
Type
I
Level
Analog
Name/Description
Limiting Amplifier Inputs (2.5 Gbits/s).
ac coupling required.
Data Output (2.5 Gbits/s NRZ).
2.5 Gbits/s differential data
output.
O
CML
I
Pins are high impedance when END2G5N = 1.
I
Pins are active but forced to differential logic low when
MUTE2G5N = 0.
Enable D2G5P/N Data Outputs (Active-Low).
0 = D2G5P/N buffer enabled
1 or no connection = D2G5P/N buffer powered off
Mute D2G5P/N Data Output (Active-Low).
0 = muted
1 or no connection = normal data
Recovered Clock Output (2.5 GHz).
2.5 GHz recovered differen-
tial clock output. Pins are high impedance when ENCK2G5N = 1.
Enable CK2G5P/N Clock Output (Active-Low).
0 = CK2G5P/N buffer enabled
1 or no connection = CK2G5P/N buffer powered off
Resistor Reference 1.
CML current bias reference resistor. (See
Table 16, page 22 for values.)
Resistor Reference 2.
CML bias reference resistor. Place a
1.5 k
resistor to V
CCD
.
Voltage Threshold Adjust Input.
This input is for monitoring
purposes only and should be left open (see Figure 3 on page 10).
Slice Level Adjustment.
Adjusts slice level for the limiting amp
(see Figure 3 on page 10).
Open Drain
Loss of Analog Signal (Active-Low).
Analog
Programming Voltage for LOSA Threshold.
Programming
voltage is scaled (see Figure 7 on page 16).
Open Drain
Loss of Digital Data (Active-Low).
CMOS
Input Loss of Signal (Active-Low).
Forces VCO to decrease to
its minimum frequency.
0 = force VCO low
1 or no connection = normal operation
Analog
Loop Filter PLL.
Connect LFP to VCP, and LFN to VCN.
122
END2G5N
I
u
CMOS
118
MUTE2G5N
I
u
CMOS
53
54
123
CK2G5P
CK2G5N
ENCK2G5N
O
CML
I
u
CMOS
41
RREF1
I
Analog
40
RREF2
I
Analog
28
34
26
VTHP
VTHN
SLADJ
I
Analog
I
Analog
119
25
LOSAN
PRG_LOSA
O
I
120
121
LOSDN
INLOSN
O
I
u
18
17
19
16
LFP
LFN
VCP
VCN
O
I
Analog
VCO Control.
Connect VCP to LFP, and VCN to LFN.
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