參數(shù)資料
型號: TRCV012G5
廠商: Lineage Power
元件分類: 運動控制電子
英文描述: Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer(2.5 Gbits/s)(限幅放大器,時鐘恢復,1:16數(shù)據(jù)多路分解器(2.5 G位/秒))
中文描述: 限幅放大器,時鐘恢復,1:16數(shù)據(jù)復用器(2.5 Gb /秒)(限幅放大器,時鐘恢復,1:16數(shù)據(jù)多路分解器(2.5摹位/秒))
文件頁數(shù): 11/28頁
文件大?。?/td> 500K
代理商: TRCV012G5
Preliminary Data Sheet
August 2000
TRCV012G5 and TRCV012G7
Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
11
Lucent Technologies Inc.
Clock and Data Recovery (CDR)
Clock Recovery Operation
The CDR circuit uses a PLL to extract the clock and retime the 2.5 Gbits/s data. The 2.5 Gbits/s data and the
2.5 GHz recovered clock are available as outputs, as well as a 155 MHz clock derived from the recovered clock.
Clock Recovery PLL Loop Filter
A typical loop filter that meets the OC-48 jitter transfer template is shown in Figure 4. Connect the filter compo-
nents and also connect LFP to VCP and connect LFN to VCN. The component values can be varied to adjust the
loop dynamic response (see Table 5).
Table 5. Clock Recovery Loop Filter Component Values
* Capacitor C1 should be either ceramic or nonpolar.
5-8061(F).a
Figure 4. Clock Recovery PLL Loop Filter Components
CDR Acquisition Time
The limiting amplifier plus CDR will acquire phase/frequency lock within 10 ms after powerup and a valid SONET
signal or a 2
23
– 1 PRBS data signal is applied.
CDR Generated Jitter
The limiting amplifier plus CDR’s generated jitter performance meets the requirements shown in Table 6. These
specifications apply to the jitter generated at the 2.5 Gbits/s recovered clock pins (CK2G5P/N) when the following
occur: no jitter is present on the input, the limiting amplifier’s input signal is within the valid level range given in
Table 9 on page 20, and the data sequence is a valid OC-48 SONET/SDH signal.
Table 6. Clock and Data Recovery Generated Jitter Specifications
* This denotes the device specification for system SONET/SDH compliance when the loop filter in Table 5 and Figure 4 is used.
Components
C1*
C2, C3
R1
R2
Values for 2 MHz Loop Bandwidth
0.47
μ
F ± 10%
10 pF ± 20%
82.5
± 5%
100 k
± 5%
Parameter
Typical
Max
(Device)
*
0.10
Unit
Generated Jitter (p-p):
Measured with 12 kHz to 20 MHz Bandpass Filter
Generated Jitter (rms):
Measured with 12 kHz to 20 MHz Bandpass Filter
0.06
UIp-p
0.008
0.01
UIrms
C
3
C
2
C
1
R
1
LFN/VCN
LFP/VCP
R
2
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