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參數(shù)資料
| 型號： | TPS56302PWPR |
| 英文描述： | SMPS Controller |
| 中文描述： | 開關電源控制器 |
| 文件頁數(shù)： | 13/34頁 |
| 文件大?。?/td> | 811K |
| 代理商： | TPS56302PWPR |
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TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289A
–
MARCH 2000
–
REVISED OCTOBER 2000
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
detailed description (continued)
deadtime control
Deadtime control prevents shoot-through current from flowing through the main power FETs during switching
transitions by actively controlling the turnon time of the MOSFET drivers. The high-side driver is not allowed
to turn on until the gate drive voltage to the low-side FET is below 1 V, and the low-side driver is not allowed
to turn on until the voltage at the junction of the 2 FETs (Vphase) is below 2 V.
current sensing
Current sensing is achieved by sampling and holding the voltage across the high-side power FET while the
high-side FET is on. The sampling network consists of an internal 60-
switch and an external hold capacitor.
Internal logic controls the turnon and turnoff of the sample/hold switch such that the switch does not turn on until
the Vphase voltage transitions high, and the switch turns off when the input to the high-side driver goes low.
Thus sampling will occur only when the high-side FET is conducting current. The voltage on the IOUT pin equals
2 times the sensed high-side voltage.
droop compensation
The droop compensation network reduces the load transient overshoot / undershoot on V
OUT
, relative to V
REF
(see the
application information
section of this document for more details). V
OUT
is programmed to a voltage
greater than V
REF
by an external resistor divider from V
OUT
to the VSENSE pin to reduce the undershoot on
V
OUT
during a low to high load transient. The overshoot during a high to low load transient is reduced by
subtracting the voltage that is on the DROOP pin from V
REF
. The voltage on the IOUT pin is divided down with
an external resistor divider, and connected to the DROOP pin.
inhibit
INHIBIT is a TTL-compatible comparator pin that is used to enable the controller. When INHIBIT is lower than
the threshold, the output drivers are low and the slow-start capacitor is discharged. When INHIBIT goes high
(above 2.1 V), the short across the slow-start capacitor is released and normal converter operation begins.
When another system logic supply is connected to the INHIBIT pin, this pin controls power sequencing by
locking out controller operation until the system logic supply exceeds the input threshold voltage of the inhibit
circuit; thus the +3.3-V supply and another system logic supply (either +5 V or +12 V) must be above UVLO
thresholds before the controller is allowed to start up. Toggling the INHIBIT pin from low to high or recycling V
CC
clears the fault latch.
slow-start
The slow-start circuit controls the rate at which both V
OUT
–
RR
and V
OUT
–
LDO
power up (at the same time). A
capacitor is connected between the SLOWST and ANAGND pins and is charged by an internal current source.
The value of the current source is proportional to the reference voltage, so that the charging rate of C
SLOWST
is proportional to the ripple regulator reference voltage. The slow-start charging current is determined by the
following equation:
ISLOWSTART
IVREFB
5
Where I
VREFB
is the current flowing out of the VREFB pin. It is recommended that no additional loads be
connected to VREFB, other than the resistor divider for setting the hysteresis voltage. Thus these resistor values
will determine the slow-start charging current. The maximum current that can be sourced by the VREFB circuit
is 500
μ
A. The equation for the slow-start time is:
TSLOWSTART
5
CSLOWSTART
RVREFB
Where R
VREFB
is the total external resistance from VREFB to ANAGND.
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