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參數(shù)資料
| 型號(hào)： | TPS54611-Q1 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 3-V TO 6-V INPUT, 6-A OUTPUT SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETs(SWIFT) |
| 中文描述： | 3 - V至6 V輸入，6 - A輸出同步降壓PWM開(kāi)關(guān)帶有集成FET協(xié)會(huì)（SWIFT） |
| 文件頁(yè)數(shù)： | 3/18頁(yè) |
| 文件大?。?/td> | 246K |
| 代理商： | TPS54611-Q1 |
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SGLS266D OCTOBER 2004 REVISED DECEMBER 2004
www.ti.com
3
Terminal Functions
TERMINAL
NAME
AGND
DESCRIPTION
NO.
1
Analog ground. Return for slow-start capacitor, VBIAS capacitor, RT resistor FSEL. Make PowerPAD connection to AGND.
Bootstrap input. A 0.022-
μ
F to 0.1-
μ
F low-ESR capacitor connected from BOOT to PH generates a floating drive for the
high-set FET driver.
BOOT
5
NC
3
No connection
PGND
1519
Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas to
the input and output supply returns and negative terminals of the input and output capacitors.
PH
614
Phase input/output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.
Power good open drain output. High-Z when VSENSE
≥
90% Vref, otherwise PWRGD is low. Note that output is low when
SS/ENA is low or internal shutdown signal active.
PWRGD
4
RT
28
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency.
SS/ENA
26
Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and
capacitor input to externally set the start-up time.
FSEL
27
Frequency select input. Provides logic input to select between two internally set switching frequencies.
VBIAS
25
Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high
quality, low-ESR 0.1-
μ
F to 1-
μ
F ceramic capacitor.
VIN
2024
Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device
package with a high quality, low-ESR 1-
μ
F to 10-
μ
F ceramic capacitor.
Error amplifier inverting input. Connect directly to output voltage sense point.
VSENSE
2
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
VIN, SS/ENA, FSEL
0.3 V to 7 V
VI
Input voltage range
RT
0.3 V to 6 V
VSENSE
0.3 V to 4 V
BOOT
0.3 V to 17 V
VO
Output voltage range
VBIAS, PWRGD
0.3 V to 7 V
PH
0.6 V to 10 V
IO
Source current
PH
Internally Limited
VBIAS
6 mA
IS
Sink current
PH
12 A
SS/ENA, PWRGD
10 mA
±
0.3 V
Voltage differential
AGND to PGND
Continuous power dissipation
See Power Dissipation Rating Table
40
°
C to 150
°
C
65
°
C to 150
°
C
300
°
C
TJ
Tstg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
Operating virtual junction temperature range
Storage temperature
(1)Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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