參數(shù)資料
型號(hào)： TPS54377RHFTG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 穩(wěn)壓器
英文描述： 7.5 A SWITCHING REGULATOR, 1600 kHz SWITCHING FREQ-MAX, PQCC24
封裝： 4 X 5 MM, GREEN, PLASTIC, QFN-24
文件頁(yè)數(shù)： 6/22頁(yè)
文件大?。?/td> 727K
代理商： TPS54377RHFTG4
www.ti.com
Power Good (PWRGD)
Dead-Time Control and MOSFET Drivers
OUTPUT VOLTAGE LIMITATIONS
V max=0.9xV min-I max[(-0.016xV min+0.184)+RL]
O
I
O
I
Overcurrent Protection
Thermal Shutdown
V min=(150E-9xV maxxFsx1.08)-I minx
O
I
o
X V max
i
+0.111+RL
([
]
)
-0.026
3
(6)
SLVS779 – SEPTEMBER 2007
low-side FET remains on until the VSENSE voltage
several milliseconds. With a persistent fault condition,
decreases
to
a
range
that
allows
the
PWM
the device cycles continuously; starting up by control
comparator to change states. The TPS54377 is
of the soft-start circuit, heating up due to the fault,
capable of sinking current continuously until the CO
and then shutting down upon reaching the thermal
reaches the regulation set-point.
shutdown point.
If the current limit comparator trips for longer than
100 ns, the PWM latch resets before the PWM ramp
exceeds the error amplifier output. The high-side FET
The power good circuit monitors for undervoltage
turns off and low-side FET turns on to decrease the
conditions on VSENSE. If the voltage on VSENSE is
energy in the output inductor, and consequently, the
10% below the reference voltage, the open-drain
output current. This process is repeated each cycle in
PWRGD output is pulled low. PWRGD is also pulled
which the current limit comparator is tripped.
low if VIN is less than the UVLO threshold, or
SS/ENA is low, or thermal shutdown is asserted.
When VIN = UVLO threshold, SS/ENA = enable
threshold, and VSENSE > 90% of Vref, the open drain
Adaptive dead-time control prevents shoot-through
output of the PWRGD pin is high. A hysteresis
current
from
flowing
in
both
N-channel
power
voltage equal to 3% of Vref and a 35-μs falling edge
MOSFETs during the switching transitions by actively
deglitch circuit prevent tripping of the power good
controlling the turn-on times of the MOSFET drivers.
comparator due to high frequency noise.
The high-side driver does not turn on until the gate
drive voltage to the low-side FET is below 2 V. The
low-side driver does not turn on until the voltage at
the gate of the high-side MOSFETs is below 2 V. The
Due to the internal design of the TPS54377, there are
high-side and low-side drivers are designed with a
both upper and lower output voltage limits for any
300-mA source and sink capability to drive the power
given input voltage. Additionally, the lower boundary
MOSFETs gates. The low-side driver is supplied from
of the output voltage set point range is also
VIN, while the high-side drive is supplied from the
dependent on operating frequency. The upper limit of
BOOT pin. A bootstrap circuit uses an external BOOT
the output voltage set point is constrained by the
capacitor and an internal 2.5-
bootstrap switch
maximum duty cycle of 90% and is given by
connected between the VIN and BOOT pins. The
integrated bootstrap switch improves drive efficiency
and reduces external component count.
(5)
Where:
VImin = minimum input voltage
The cycle by cycle current limiting is achieved by
IOmax = maximum load current
sensing the current flowing through the high-side
RL = series resistance of the output inductor
MOSFET and differential amplifier, and comparing it
to the preset overcurrent threshold. The high-side
Equation 5 assumes maximum on resistance for the
MOSFET is turned off within 200 ns of reaching the
internal high-side and low-side FETs.
current limit threshold. A 100-ns
leading
edge
The lower limit is constrained by the minimum
blanking circuit prevents false tripping of the current
controllable on time which may be as high as 150 ns.
limit. Current limit detection occurs only when current
The approximate minimum output voltage for a given
flows from VIN to PH when sourcing current to the
input voltage, operating frequency, and minimum load
output filter. Load protection during current sink
current is given in Equation 6:
operation is provided by thermal shutdown.
The device uses the thermal shutdown to turn off the
power MOSFETs and disable the controller if the
junction temperature exceeds 150
°C. The device is
Where:
released
from
shutdown
when
the
junction
VI = maximum input voltage
temperature decreases to 10
°C below the thermal
Fs = programmed operating frequency
shutdown trip point and starts up under control of the
slow-start
circuit.
Thermal
shutdown
provides
IO = minimum load current
protection when an overload condition is sustained for
RL = series resistance of the output inductor
14
Copyright 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS54377
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