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參數(shù)資料
| 型號： | TPS54377RHFTG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 7.5 A SWITCHING REGULATOR, 1600 kHz SWITCHING FREQ-MAX, PQCC24 |
| 封裝： | 4 X 5 MM, GREEN, PLASTIC, QFN-24 |
| 文件頁數(shù)： | 4/22頁 |
| 文件大小： | 727K |
| 代理商： | TPS54377RHFTG4 |
www.ti.com
V =50mV/div
(ACCoupled)
I
PH=2V/div
500ns/div
-0.2
3
4
5
OutputRegulation
%
-0.1
0.3
6
0.1
0
0.2
-0.3
V InputVoltage
I
V
I =0 A
O
I =1.5 A
O
I =3 A
O
0
10
20
30
50
40
60
80
70
90
100
120
110
130
0
0.5
1
1.5
2
2.5
3
AmbientT
emperature
IL LoadCurrent A
C
°
T
A
SafeOperating Area
Safe
tothetest
boardconditionslistedinthedissipation
ratingtablesectionofthisdatasheet.
operatingareaisapplicable
f =700kHz
V =5V
V =3.3V
T =125 C
s
I
O
J
o
DETAILED DESCRIPTION
Disabled Sinking During Start-Up (DSDS)
Undervoltage Lock Out (UVLO)
t
d +
C
(SS)
1.2 V
5 mA
(2)
t
(SS) +
C
(SS)
0.7 V
5 mA
(3)
Slow-Start/Enable (SS/ENA)
SLVS779 – SEPTEMBER 2007
TA = 25°C, fs = 1.1 MHz, VI = 3.3 V, VO = 1.8 V (unless otherwise specified)
AMBIENT TEMPERATURE
LINE REGULATION
vs
LOAD CURRENT
INPUT RIPPLE VOLTAGE
INPUT VOLTAGE
Figure 19.
Figure 20.
Figure 21.
the error amplifier is linearly ramped up from 0 V to
0.891 V in 3.35 ms. Similarly, the converter output
voltage reaches regulation in approximately 3.35 ms.
Voltage hysteresis and a 2.5-
μs falling edge deglitch
circuit reduce the likelihood of triggering the enable
The DSDS feature enables minimal voltage drooping
due to noise.
of output precharge capacitors at start-up. The
The second function of the SS/ENA pin provides an
TPS54373 is designed to disable the low-side
external means of extending the slow-start time with
MOSFET to prevent sinking current from a precharge
a low-value capacitor connected between SS/ENA
output capacitor during start-up. Once the high-side
and AGND. Adding a capacitor to the SS/ENA pin
MOSFET has been turned on to the maximum duty
has two effects on start-up. First, a delay occurs
cycle limit, the low-side MOSFET is allowed to switch.
between release of the SS/ENA pin and start up of
Once the maximum duty cycle condition is met, the
the output. The delay is proportional to the slow-start
converter functions as a sourcing converter until the
capacitor value and lasts until the SS/ENA pin
SS/ENA is pulled low.
reaches the enable threshold. The start-up delay is
approximately:
The TPS54377 incorporates an undervoltage lockout
circuit to keep the device disabled when the input
voltage (VIN) is insufficient. During power up, internal
Second, as the output becomes active, a brief
circuits are held inactive until VIN exceeds the
ramp-up at the internal slow-start rate may be
nominal UVLO threshold voltage of 2.95 V. Once the
observed before the externally set slow-start rate
UVLO start threshold is reached, device start-up
takes
control
and
the
output
rises
at
a
rate
begins. The device operates until VIN falls below the
proportional to the slow-start capacitor. The slow-start
nominal UVLO stop threshold of 2.8 V. Hysteresis in
time set by the capacitor is approximately:
the UVLO comparator, and a 2.5-s rising and falling
edge deglitch circuit reduce the likelihood of shutting
the device down due to noise on VIN.
The actual slow-start is likely to be less than the
above approximation due to the brief ramp-up at the
The slow-start/enable pin provides two functions; first,
internal rate.
the pin acts as an enable (shutdown) control by
keeping the device turned off until the voltage
exceeds the start threshold voltage of approximately
1.2 V. When SS/ENA exceeds the enable threshold,
device start up begins. The reference voltage fed to
12
Copyright 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS54377
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