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參數(shù)資料
| 型號： | TPS54062DGKR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING REGULATOR, 400 kHz SWITCHING FREQ-MAX, PDSO8 |
| 封裝： | PLASTIC, MSOP-8 |
| 文件頁數(shù)： | 8/30頁 |
| 文件大?。?/td> | 745K |
| 代理商： | TPS54062DGKR |
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OUT
IN
OUT
O
IN
O
SW
V
V max
V
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IC rms =
V max
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12
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RIPPLE
O
RIPPLE
SW
I
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C 1
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SLVSAV1
– MAY 2011
Output Capacitor
There are three primary considerations for selecting the value of the output capacitor. The output capacitor will
determine the modulator pole, the output voltage ripple, and how the regulator responds to a large change in
load current. The output capacitance needs to be selected based on the more stringent of these three criteria.
The desired response to a large change in the load current is the first criteria. The output capacitor needs to
supply the load with current when the regulator can not. This situation would occur if there are desired hold-up
times for the regulator where the output capacitor must hold the output voltage above a certain level for a
specified amount of time after the input power is removed. The regulator also will temporarily not be able to
supply sufficient output current if there is a large, fast increase in the current needs of the load such as
transitioning from no load to a full load. The regulator usually needs two or more clock cycles for the control loop
to see the change in load current and output voltage and adjust the duty cycle to react to the change. The output
capacitor must be sized to supply the extra current to the load until the control loop responds to the load change.
The output capacitance must be large enough to supply the difference in current for 2 clock cycles while only
allowing a tolerable amount of droop in the output voltage. Equation 14 shows the minimum output capacitance
necessary to accomplish this. Where
ΔIout is the change in output current, sw is the regulators switching
frequency and
ΔVout is the allowable change in the output voltage.
For this example, the transient load response is specified as a 4% change in Vout for a load step from 0A (no
load) to 50 mA (full load). For this example,
ΔIOUT = 0.05-0 = 0.05 and ΔVOUT = 0.04 × 3.3 = 0.132.
Using these numbers gives a minimum capacitance of 1.89
F. This value does not take the ESR of the output
capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to
ignore in this calculation. Aluminum electrolytic and tantalum capacitors have higher ESR that should be taken
into account. The low side FET of the regulator emulates a diode so it can not sink current so any stored energy
in the inductor will produce an output voltage overshoot when the load current rapidly decreases, see Figure 27.
The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high
load current to a lower load current. The excess energy that gets stored in the output capacitor will increase the
voltage on the capacitor. The capacitor must be sized to maintain the desired output voltage during these
transient periods. Equation 13 is used to calculate the minimum capacitance to keep the output voltage
overshoot to a desired value. Where L is the value of the inductor, IOH is the output current under heavy load, IOL
is the output under light load, VF is the final peak output voltage, and Vi is the initial capacitor voltage. For this
example, the worst case load step will be from 50 mA to 0A. The output voltage will increase during this load
transition and the stated maximum in our specification is 4% of the output voltage. This will make VF = 1.04
× 3.3
= 3.432 V. Vi is the initial capacitor voltage which is the nominal output voltage of 3.3 V. Using these numbers in
Equation 14 yields a minimum capacitance of 0.619
F.
Equation 12 calculates the minimum output capacitance needed to meet the output voltage ripple specification.
Where fSW is the switching frequency, Voripple is the maximum allowable output voltage ripple, and Iripple is the
inductor ripple current. Equation 13 yields 0.671
F. Equation 15 calculates the maximum ESR an output
capacitor can have to meet the output voltage ripple specification. Equation 15 indicates the ESR should be less
than 0.466
Ω.
The most stringent criteria for the output capacitor is 1.89
F of capacitance to keep the output voltage in
regulation during an load transient.
Additional capacitance de-ratings for aging, temperature and dc bias should be factored in which will increase
this minimum value. For this example, 10
F, 10V X5R ceramic capacitor with 0.003 Ω of ESR will be used.
Capacitors generally have limits to the amount of ripple current they can handle without failing or producing
excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor
data sheets specify the Root Mean Square (RMS) value of the maximum ripple current.
Equation 11 can be used to calculate the RMS ripple current the output capacitor needs to support. For this
application, Equation 11 yields 10.23 mA.
(11)
(12)
16
Copyright
2011, Texas Instruments Incorporated
Product Folder Link(s): TPS54062
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