參數(shù)資料
型號(hào): TPS40040DRBT
廠商: TEXAS INSTRUMENTS INC
元件分類: 穩(wěn)壓器
英文描述: 7.2 A SWITCHING CONTROLLER, 350 kHz SWITCHING FREQ-MAX, PDSO8
封裝: 3 X 3 MM, PLASTIC, SON-8
文件頁數(shù): 4/38頁
文件大?。?/td> 741K
代理商: TPS40040DRBT
www.ti.com
Pre-Bias Startup
t Time 2
s/div
VHDRV
VLDRV
t Time 500
s/div
VIN = 5 V
VOUT = 1.2 V
(200 mV/div)
PREBIAS = 0 V
PREBIAS = 0.5 V
PREBIAS = 1 V
SLUS700D – MARCH 2006 – REVISED DECEMBER 2007
The TPS40040/1 supports pre-biased output voltage applications. In cases where the output voltage is held up
by external means while the TPS40040/1 is off, full synchronous rectification is disabled during the initial phase
of soft starting the output voltage. When the first PWM pulses are detected during soft start, the controller slowly
initiates synshronous rectification by starting the synchronous rectifier with a narrow on time. It then increments
that on time on a cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle
of the converter. This approach prevents the sinking of current from a pre-biased output, and ensures the output
voltage startup and ramp to regulation is smooth and controlled.
NOTE:
If the output is pre-biased, PWM pulses start when the internal soft-start voltage rises
above the error amplifier input (FB pin).
Figure 20 below depicts the waveform of the HDRV and LDRV output signals at the beginning PWM pulses.
When HDRV turns off, diode rectification is enabled. Before the next PWM cycle starts, LDRV is turned on for a
short pulse. With every clock cycle, the leading edge of LDRV is modulated, increasing the on time of the
synchronous rectifier. Eventually, the leading edge of LDRV coincides with the falling edge of HDRV to achieve
full synchronous rectification. During normal operation of the converter, the TPS40040/1 operates in full two
quadrant source/sink mode.
Figure 21 shows the startup waveform of a 1.2-V output converter under three different pre-biased output
conditions. The lowest trace is when there is no pre-bias on the output. The center and top most traces indicate
converter startup with 0.5-V and 1.0-V pre-bias conditions.
Figure 20. MOSFET Drivers at Beginning of Soft Start
Figure 21. Startup Waveforms
The recommended output voltage pre-bias range is less than or equal to 90% of the final regulation voltage. A
pre-biased output voltage of 90% to 100% of final regulation could lead to the sinking of current from the pre-bias
source. If the pre-biased voltage is greater than the designed converter output regulation voltage, then upon the
completion of the soft-start interval, the TPS40040/1 draws current from the output to bring the output voltage
into regulation.
12
Copyright 2006–2007, Texas Instruments Incorporated
Product Folder Link(s): TPS40040 TPS40041
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