參數(shù)資料
型號(hào): TPS3619
廠商: Texas Instruments, Inc.
英文描述: BACKUP-BATTERY SUPERVISORS FOR RAM RETENTION(用于RAM數(shù)據(jù)保持的后備電源監(jiān)控器)
中文描述: 備用電池RAM保持監(jiān)督員(用于內(nèi)存數(shù)據(jù)保持的后備電源監(jiān)控器)
文件頁(yè)數(shù): 8/13頁(yè)
文件大?。?/td> 249K
代理商: TPS3619
SLVS387B
APRIL 2001
REVISED DECEMBER 2002
8
www.ti.com
timing requirements at R
L
= 1 M
, C
L
= 50 pF, T
A
=
40
°
C to 85
°
C
PARAMETER
TEST CONDITIONS
VIL = VIT
0.2 V
MIN
TYP
MAX
UNIT
μ
s
ns
tw
Pulse width
at VDD
at MR
VIH = VIT + 0.2 V,
VDD = VIT + 0.2 V, VIL = 0.3 x VDD, VIH = 0.7 x VDD
6
100
switching characteristics at R
L
= 1 M
, C
L
= 50 pF, T
A
=
40
°
C to 85
°
C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
td
Delay time
VDD
VIT + 0.2 V, MR
0.7 x VDD,
See timing diagram
60
100
140
ms
VDD to RESET
PFI to PFO delay
VIL = VIT
0.2 V,
VIL = VPFI
0.2 V, VIH = VPFI + 0.2 V
VDD
VIT + 0.2 V, VIL = 0.3 x VDD,
VIH = 0.7 x VDD
VIH = VIT + 0.2 V
2
5
tPHL
Propagation (delay) time,
high-to-low level output
3
5
μ
s
MR to RESET
0.1
1
TYPICAL CHARACTERISTICS
Figure 2
500
600
700
800
900
1000
50
75
100
125
150
175
200
TA = 85
°
C
TA = 25
°
C
TA = 0
°
C
TA =
40
°
C
rD
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
(V
DD
to V
OUT
)
vs
OUTPUT CURRENT
VDD = 3.3 V
VBAT = GND
IO
Output Current
mA
Figure 3
5
10
15
20
2.5
4.5
6.5
8.5
10.5
12.5
14.5
TA = 85
°
C
TA = 25
°
C
TA = 0
°
C
TA =
40
°
C
rD
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
(V
BAT
to V
OUT
)
vs
OUTPUT CURRENT
IO
Output Current
mA
VBAT = 3.3 V
7.5
12.5
17.5
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