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參數(shù)資料
| 型號： | TPS3600D50PWR |
| 英文描述： | Analog IC |
| 中文描述： | 模擬IC |
| 文件頁數(shù)： | 7/16頁 |
| 文件大小： | 214K |
| 代理商： | TPS3600D50PWR |
TPS3600D20, TPS3600D33, TPS3600D50
BATTERY-BACKUP SUPERVISORS FOR LOW-POWER PROCESSORS
SLVS336 – DECEMBER 2000
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
detailed description (continued)
25
μ
s
200 ms
100
μ
A
t
I
Figure 1. BATTOK Timing
chip-enable signal gating
The internal gating of chip-enable (CE) signals prevents erroneous data from corrupting CMOS RAM during
an under-voltage condition. The TPS3600 use a series transmission gate from CEIN to CEOUT. During normal
operation (reset not asserted), the CE transmission gate is enabled and passes all CE transitions. When reset
is asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS RAM. The short
CE propagation delay from CEIN to CEOUT enables the TPS3600 devices to be used with most processors.
The CE transmission gate is disabled and CEIN is high impedance (disable mode) while reset is asserted.
During a power-down sequence when V
DD
crosses the reset threshold, the CE transmission gate will be
disabled and CEIN immediately becomes high impedance if the voltage at CEIN is high. If CEIN is low during
reset is asserted, the CE transmission gate will be disabled same time when CEIN goes high, or 10
μ
s after reset
asserts, whichever occurs first. This will allow the current write cycle to complete during power down. When the
CE transmission gate is enabled, the impedance of CEIN appears as a 50-
resistor in series with the load at
CEOUT. To achieve minimum propagation delay, the capacitive load at CEOUT should be minimized, and a
low-output-impedance driver be used.
During disable mode, the transmission gate is off and an active pullup connects CEOUT to V
OUT
. This pullup
turns off when the transmission gate is enabled.
VDD
VBAT
V(BOK)
V(SWP)
V(SWN)
1VIT
CEIN
VDD
VBAT
V(BOK)
V(SWP)
V(SWN)
VIT
COUT
RESET
V(SWN)
VIT
10
μ
s
10
μ
s
td
td
td
Undefined Behavior
Figure 2. Chip-Enable Timing
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| TPS3600D50PWRG4 | 功能描述:監(jiān)控電路 Battery-Backup for LP Processor RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| TPS3600EVM-186 | 功能描述:電源管理IC開發(fā)工具 TPS3600-186 Eval Mod RoHS:否 制造商:Maxim Integrated 產(chǎn)品:Evaluation Kits 類型:Battery Management 工具用于評估:MAX17710GB 輸入電壓: 輸出電壓:1.8 V |
| TPS3600X20PW | 制造商:TI 制造商全稱:Texas Instruments 功能描述:BATTERY-BACKUP SUPERVISORS FOR LOW-POWER PROCESSORS |
| TPS3600X20PWR | 制造商:TI 制造商全稱:Texas Instruments 功能描述:BATTERY-BACKUP SUPERVISORS FOR LOW-POWER PROCESSORS |
| TPS3600X25PW | 制造商:TI 制造商全稱:Texas Instruments 功能描述:BATTERY-BACKUP SUPERVISORS FOR LOW-POWER PROCESSORS |
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