參數(shù)資料
型號： TPS3600D50PWR
英文描述： Analog IC
中文描述： 模擬IC
文件頁數(shù)： 12/16頁
文件大?。?/td> 214K
代理商： TPS3600D50PWR
TPS3600D20, TPS3600D33, TPS3600D50
BATTERY-BACKUP SUPERVISORS FOR LOW-POWER PROCESSORS
SLVS336 – DECEMBER 2000
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VO = 2.0 V, IOH = –400
μ
A
VO = 3.3 V, IOH = –2 mA
VO = 5.0 V, IOH = –3 mA
VO = 1.8 V, IOH = –20
μ
A
VO = 3.3 V, IOH = –80
μ
A
VO = 5.0 V, IOH = –120
μ
A
VO = 2.0 V, IOH = –1 mA
VO = 3.3 V, IOH = –2 mA
VO = 5.0 V, IOH = –5 mA
MIN
TYP
MAX
UNIT
RESET
BATTOK
BATTON
VOUT – 0.2 V
VOUT – 0.4 V
VOUT – 0.3 V
VOH
High-level output
voltage
PFO
VOUT – 0.4 V
V
CEOUT
Enable mode
CEIN = VOUT
CEOUT
Disable mode
RESET
PFO
BATTOK
VOUT – 0.2 V
VOUT – 0.3 V
VO = 3.3 V, IOH = –0.5 mA
VOUT – 0.4 V
VO = 2.0 V, IOL = 400
μ
A
VO = 3.3 V, IOL = 2 mA
VO = 5.0 V, IOL = 3 mA
VO = 1.8 V, IOL = 500
μ
A
VO = 3.3 V, IOL = 3 mA
VO = 5.0 V, IOL = 5 mA
VO = 2.0 V, IOL = 1 mA
VO = 3.3 V, IOL = 2 mA
VO = 5.0 V, IOL = 5 mA
VBAT > 1.1 V OR
VDD > 1.4 V, IOL = 20
μ
A
IO = 5 mA, VDD = 1.8 V
IO = 75 mA, VDD = 3.3 V
IO = 150 mA, VDD = 5 V
IO = 4 mA, VBAT = 1.5 V
IO = 75 mA, VBAT = 3.3 V
VDD = 3.3 V
VBAT = 3.3 V
0.2
0 4
0.4
Low-level output
voltage
0.2
VOL
BATTON
0.4
V
CEOUT
Enable mode
CEIN = 0 V
0.2
0.3
Vres
Power-up reset voltage (see Note 2)
0.4
V
VDD – 50 mV
VDD – 150 mV
VDD – 250 mV
VBAT – 50 mV
VBAT – 150 mV
Normal mode
VO
V
Battery backup mode
Battery-backup mode
rd (
rds(on)
VDD to VO on-resistance
VBAT to VO on-resistance
1
1
2
2
TPS3600x20
TPS3600x25
TPS3600x30
TPS3600x33
TPS3600x50
PFI
TPS3600Dxx
1.74
2.17
2.57
2.87
4.31
1.13
VIT + 5.8%
1.78
2.22
2.63
2.93
4.40
1.15
1.82
2.27
2.69
2.99
4.49
1.17
V
V
V
V
V
VIT
Negative-going input
Negative-going in ut
threshold voltage
(see Notes 3 and 4)
°
C to 85
°
C
TA = –40
V(PFI)
V(BOK)
VIT + 7.1%
VIT + 8.3%
V(SWN)
Battery switch threshold voltage
negative-going VO
2. The lowest supply voltage at which RESET becomes active. tr(VDD)
≥
15
μ
s/V.
3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1
μ
F) should be placed near the supply terminal.
4. Voltage is sensed at VO
VIT + 1%
VIT + 2%
VIT + 3.2%
V
NOTES:
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