參數(shù)資料
型號(hào)： TPS2459RHBR
廠商： TEXAS INSTRUMENTS INC
元件分類： 電源管理
英文描述： 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC32
封裝： PLASTIC, QFP-32
文件頁(yè)數(shù)： 8/44頁(yè)
文件大小： 983K
代理商： TPS2459RHBR
PRODUCTPREVIEW
SLUS917 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com
Summary of Registers
Table 2. Summary of Registers
BIT
NAME
DEFAULT
DESCRIPTION
REGISTER 3 READ/WRITE
12-V CHANNEL CONFIGURATION
0
12CL0
1
Clearing bit reduces 12-V current limit and fast threshold by 5%.
1
12CL1
1
Clearing bit reduces 12-V current limit and fast threshold by 10%.
2
12CL2
1
Clearing bit reduces 12-V current limit and fast threshold by 20%.
3
12CL3
1
Clearing bit reduces 12-V current limit and fast threshold by 40%.
4
12PG0
1
Clearing bit reduces 12-V power good threshold by 600 mV.
5
12PG1
1
Clearing bit reduces 12-V power good threshold by 1.2 V.
6
12HP
0
Setting bit shifts 12 OR VTURNOFF from –3 mV to +3 mV nominal.
7
12OR
1
Clearing bit turns off 12-V ORing FET by pulling BLK low.
REGISTER 4 READ/WRITE
12-V CHANNEL CONFIGURATION
0
12FT0
1
Setting bit increases 12-V fault time by 0.5 ms.
1
12FT1
0
Setting bit increases 12-V fault time by 1 ms.
2
12FT2
0
Setting bit increases 12-V fault time by 2 ms.
3
12FT3
0
Setting bit increases 12-V fault time by 4 ms.
4
12FT4
0
Setting bit increases 12-V fault time by 8 ms.
5
12EN
0
Clearing bit disables 12-V by pulling PASSB and BLKB to 0 V.
6
12UV
0
Setting bit prevents enabling unless OUT12 < bleed-down threshold.
7
12DS
0
Clearing bit disconnects OUT12 bleed-down resistor.
REGISTER 5 READ/WRITE
3.3-V CHANNEL CONFIGURATION
0
3FT0
1
Setting bit increases 3 V fault time by 0.5 ms.
1
3FT1
0
Setting bit increases 3 V fault time by 1 ms.
2
3FT2
0
Setting bit increases 3 V fault time by 2 ms.
3
3FT3
0
Setting bit increases 3 V fault time by 4 ms.
4
3FT4
0
Setting bit increases 3 V fault time by 8 ms.
5
3EN
0
Clearing bit disables 3 V.
6
3UV
0
Setting bit prevents enabling unless OUT3B < bleed-down threshold.
7
3DS
0
Clearing bit disconnects OUT3B bleed-down resistor.
REGISTER 6 READ/WRITE
SYSTEM CONFIGURATION
0
PPTEST
0
12-V pulldown test pin. Setting pin pulls the PASS and BLK pins to 0 V.
Clearing bit latchs off channels after over-current fault. Setting bit allows channels to
1
FLTMODE
0
automatically attempt restart after fault.
2
ENPOL
0
Setting bit makes EN3 and EN12 pins active low.
3
3ORON
0
Setting bit enables 3-V channel to prevent reverse current flow.
Non Redundant System in rush control bit. Setting bit allows increased inrush current in
4
12VNRS
0
12-V channel .
5
DISA
0
This bit must be set to 1
6
spare
0
Setting bit allows the 12-V channels to operate despite loss of 3.3-V. This bit should be low
7
DCC
0
for
TCA and AMC applications
16
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS2459
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