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| 型號： | TPS2459RHBR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC32 |
| 封裝： | PLASTIC, QFP-32 |
| 文件頁數(shù)： | 10/44頁 |
| 文件大?。?/td> | 983K |
| 代理商： | TPS2459RHBR |
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PRODUCTPREVIEW
DETAILED DESCRIPTION OF REGISTERS
SLUS917 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com
Table 3. Register 3: 12-V Channel Configuration (Read/Write)
BIT
NAME
DEFAULT
DESCRIPTION
0
12CL0
1
Clearing bit reduces 12-V current limit and fast threshold by 5%.
1
12CL1
1
Clearing bit reduces 12-V current limit and fast threshold by 10%.
2
12CL2
1
Clearing bit reduces 12-V current limit and fast threshold by 20%.
3
12CL3
1
Clearing bit reduces 12-V current limit and fast threshold by 40%.
4
12PG0
1
Clearing bit reduces 12-V power good threshold by 600 mV.
5
12PG1
1
Clearing bit reduces 12-V power good threshold by 1.2 V.
6
12HP
0
Setting bit shifts 12-V OR VTURNOFF from –3 mV to +3 mV nominal.
7
12OR
1
Clearing bit turns off 12-V ORing FET by pulling BLK low.
12CL[3:0]
These four bits adjust the 12-V current limit and fast trip threshold using the I2CTM interface. Setting the bits to 1111B places
the 12-V current limit at its maximum level, corresponding to 675 mV at SUM12. The fast trip threshold then equals 100 mV.
Clearing all bits reduces the current limit and fast trip threshold to 25% of these maximums.
12PG[1:0]
These two bits adjust the 12-V power good threshold. Setting the bits to 11B places the power good threshold at its maximum
level of 10.5 V . Setting the bits to 00B places the threshold at its minimum level of 8.7 V. The lower thresholds may prove
desirable in systems that routinely experience large voltage droops.
12HP
Setting this bit moves the 12-V ORing turn off threshold from –3 mV to +3 mV. A positive threshold prevents reverse current
from flowing through the channel, but it may cause the ORing FET to repeatedly cycle on-and-off if the load is too light to
maintain the required positive voltage drop across the combined resistance of the external FETs and the sense resistor. For
further information, see Adjusting ORing Turn Off Threshold For High Power Loads section.
12OR
Clearing this bit forces the BLK pin low, keeping the 12-V ORing FET off. Clearing this bit does not prevent current from
flowing through the FET’s body diode.
.
Table 4. Register 4: 12-V Channel Configuration (Read/Write)
BIT
NAME
DEFAULT
DESCRIPTION
0
12FT0
1
Setting bit increases 12-V fault time by 0.5 ms.
1
12FT1
0
Setting bit increases 12-V fault time by 1 ms.
2
12FT2
0
Setting bit increases 12-V fault time by 2 ms.
3
12FT3
0
Setting bit increases 12-V fault time by 4 ms.
4
12FT4
0
Setting bit increases 12-V fault time by 8 ms.
5
12EN
0
Clearing bit disables 12-V by pulling PASS and BLK to 0 V.
6
12UV
0
Setting bit prevents enabling unless OUT12 < bleed-down threshold.
7
12DS
0
Clearing bit disconnects OUT12 bleed-down resistor.
12FT[4:0]
These five bits adjust the 12-V channel fault time. The least-significant bit has a nominal weight of 0.5 ms, so fault times
ranging from 0.5 ms (for code 00001B) to 15.5 ms (for code 11111B) can be programmed. In general the shortest fault time
that fully charges downstream bulk capacitors without generating a fault should be used. Once the load capacitors have fully
charged, the fault time can be reduced to provide faster short circuit protection. See Setting Fault Time section.
12EN
This bit serves as a master enable for the 12-V channel. Setting the bit allows the 12-V channel to operate normally. Clearing
the bit disables the channel by pulling PASS and BLK low.
12UV
Setting this bit prevents 12-V channel from turning on until VOUT12 falls below the bleed-down threshold of 100 mV. This
feature ensures that downstream devices reset by requiring their supply voltage to fall to nearly zero before the channel can
enable them.
12DS
Clearing this bit disconnects the bleed-down resistor that otherwise connects from OUT12 to ground. Systems using
redundant power supplies should clear 12DS to prevent the bleed-down resistor from continuously sinking current.
.
18
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS2459
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