參數(shù)資料
型號(hào): TPS2350EVM
廠商: Texas Instruments, Inc.
英文描述: TPS2350 -48V Hot Swap/Supply Selector Evaluation Module(’-48V熱交換/電源選擇器TPS2350的評(píng)估板)
中文描述: TPS2350 - 48V熱插拔/供應(yīng)選擇評(píng)估模塊(\u0026#39;- 48V的熱交換/電源選擇器TPS2350的評(píng)估板)
文件頁(yè)數(shù): 18/20頁(yè)
文件大?。?/td> 375K
代理商: TPS2350EVM
SLUU171A - September 2003
18
TPS2350 48-V Hot Swap/Supply Selector Evaluation Module
4.6
Fault Timing with the TPS2350
Whenever the hot swap controller is limiting current to the load, an on-chip timer is monitoring this operation
against an established time limit. The timeout period is generated by the constant-current charging of a capacitor
at the FLTTIM pin. If current regulation ceases prior to expiration of the timer, the capacitor is discharged, and
normal steady-state operation of the load either starts or resumes. However, if the timer expires, then the pass
FET is turned off, disabling power to the load, and the FAULT output is asserted.
On the TPS2350 48-V hot swap/supply selector EVM, several capacitor patterns are provided for adding to
or otherwise modifying the timeout period. Capacitor C6 is hard-wired to the device FLTTIM pin, and provides
a minimum fault timer for the default load. C4 and C5 can be switched into the circuit via DIP switches SW14
and SW15, respectively. The EVM ships from the factory with a 0.1-
μ
F capacitor installed at C4; C5 is not
populated for easier subsequent user modification as required.
If the target application requires fault timing other than provided by the default EVM setup, a new value of timing
capacitor can be calculated from equation 3. When selecting from the readily available capacitor values for the
equation 3 result, default to a slightly larger, rather than smaller, capacitor.
C
FLT
54
t
FLT
3.75
where:
C
FLT
is the calculated value in microfarads, and
t
FLT
is the desired timeout period in seconds
4.7
Programming the UVLO and OVLO Thresholds and Hysteresis
The UV and OV pins can be used to set the circuit undervoltage and overvoltage thresholds (V
UV
and V
OV
,
respectively). When the input supply is below V
UV
or above V
OV
, the GAT pin is held low, disconnecting power
from the load, and the PG output is deasserted. When input voltage is within the UV/OV window, the GAT drive
is enabled, assuming all other input conditions are valid for turn-on.
Threshold hysteresis is also externally programmable. Internal current sources are switched to the UV and OV
pins whenever the corresponding input voltage exceeds the nominal 1.4-V reference.
On the EVM, the V
UV
and V
OV
thresholds are individually programmed via the three-resistor divider R1, R2, and
R3 (refer to Figure 2). The factory-installed resistor values result in the following nominal voltage thresholds.
Table 8. Nominal UVLO and OVLO settings.
PARAMETER
DESCRIPTION
VALUE (V)
VUV_L
VUV_H
VOV_L
VOV_H
UVLO threshold, supply low (VIN < VUV)
UVLO threshold, supply high (VIN > VUV)
OVLO threshold, supply low (VIN < VOV)
OVLO threshold, supply high (VIN > VOV)
32.8
30.8
72.6
70.5
(3)
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