參數(shù)資料
型號: TPS2350EVM
廠商: Texas Instruments, Inc.
英文描述: TPS2350 -48V Hot Swap/Supply Selector Evaluation Module(’-48V熱交換/電源選擇器TPS2350的評估板)
中文描述: TPS2350 - 48V熱插拔/供應(yīng)選擇評估模塊(\u0026#39;- 48V的熱交換/電源選擇器TPS2350的評估板)
文件頁數(shù): 13/20頁
文件大?。?/td> 375K
代理商: TPS2350EVM
SLUU171A - September 2003
13
TPS2350 48-V Hot Swap/Supply Selector Evaluation Module
3.2.2
Functional Test
Turn on all the power supplies.
On the EVM, place the POWER switch in the ON position. Verify the FAULT LED (D1) remains off. Verify the
voltage readings in Table 4 are obtained at the corresponding test points.
Table 4. Test Point Voltages Outputs OFF
TEST POINT
REFERENCE
VOLTAGE READING
0
±
200 mV
250 mV max.
TP22
TP24/TP25
J7
TP24/TP25
Place the ENABLE switch in the ON position. Verify the FAULT LED (D1) remains off. The oscilloscope should
have acquired a sweep similar to that shown in Figure 5.
t Time 10 ms/div
CH. 2
2 V/div
CH. 3
5 V/div
CH. 1
2 V/div
CH. 4
20 V/div
VOUT
FLTTIM
RAMP
UV
Figure 5.
Load Ramp-Up Waveform
The brief fault timing ramp which is shown in Figure 5 (FLTTIM trace) may or may not be present, depending
on the actual values of the timing parameters for the particular board being used. If the load voltage ramps to
full input potential during the initial reduced rate ramp period, then fault timing does not initiate.
The DMM can now be used to verify that the voltages shown in Table 5 are present at the test points indicated.
Table 5. Test Point Voltages Outputs ON
TEST POINT
REFERENCE
VOLTAGE READING
TP22
TP24/TP25
~ Input Supply Voltage
J7
TP24/TP25
4.93 V min.
TP3
TP7
Approx. 2.13 V
TP4
TP7
Approx. 0.94 V
Leave a meter connected across TP22 and TP24/TP25 (i.e., the VOUT terminals). Decrease the voltage of the
PS No. 1 supply to be less than 43.5 V. Verify that as the supply is decreased below this voltage, the VOUT
voltage remains at the PS No. 2 potential, about 44 V.
Place either the ENABLE or POWER switch (or both) in the OFF position to remove power from the VOUT
terminals.
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