參數(shù)資料
型號(hào): TPS2341PHPR
廠商: TEXAS INSTRUMENTS INC
元件分類: 電源管理
英文描述: 4-CHANNEL POWER SUPPLY SUPPORT CKT, PQFP48
封裝: POWERPAD, HTQFP-48
文件頁數(shù): 8/31頁
文件大?。?/td> 649K
代理商: TPS2341PHPR
TPS2341
SLUS513A MAY 2003 REVISED JULY 2004
16
www.ti.com
APPLICATION INFORMATION
Interrupt Service Request
The TPS2341 generates an interrupt by asserting the IRQ# output. Any of the following conditions causes an
interrupt:
D The SWx input changes state.
D An auxiliary or main output over-current fault occurs.
D A main input/output under-voltage condition occurs.
D Thermal shutdown of the TPS2341 occurs.
The status registers (see Table 1) can be read to determine the cause of the interrupt and to identify the slot
causing the interrupt.
Slot level control of an interrupt is possible through the interrupt mask in register 00h. For example, setting mask
bits zero and two to logic 1 and logic 0, respectively, enables a slot A interrupt but disables a slot B interrupt.
These mask bits only affect the IRQ# output pin, the internal IRQ bits in register 10h still acknowledge the fault.
Resetting the Interrupt
A SWx input state change causes an interrupt that is cleared by setting bit 4 (SW interrupt reset) of register 00h
to logic 1. This bit must then be set to logic 0 to rearm the interrupt.
An interrupt that is caused by an overload on the auxiliary channel will be cleared along with the fault when the
SWx input pin is brought high (disable) or the PGOOD input pin is brought low.
An interrupt that is caused by an overload on the main channel or a main input/output undervoltage condition
will be cleared along with the fault when the ENx input pin is brought low and the ENx bit in register 00h is brought
low. This interrupt is also cleared when the PGOOD input is brought low.
I2C Operation
The TPS2341 communicates with the master controller using the I2C serial protocol. The SCL pin, which is the
clock, and the SDA pin, which is the bi-directional data, are used for transferring data to and from the device.
The TPS2341 implements a 7-bit addressing scheme with the upper six bits internally defined 010000 and the
least significant bit user programmable with the ADDR1 pin.
The data protocol recognizes a START pulse as a high-to-low transition on the SDA pin when the SCL pin is
high. The rising edge of the SCL pin clocks a logic-high into (or out of) the device when SDA is high and a
logic-low when the SDA pin is low. An ACKNOWLEDGE handshake occurs as the device receiving the 8-bit
word pulls the SDA pin low when the SCL pin is clocked the ninth time. Another 8-bit word followed by an
ACKNOWLEDGE bit can immediately begin depending upon the read or write cycle protocol.
The write cycle protocol begins with a START bit, contains three 8-bit words, each followed by an
ACKNOWLEDGE bit and ends with a STOP bit. The first 8-bit word is the device address which must match
the internally defined upper 6 bits and externally defined least significant bit with a low LSB (A0) to indicate a
write cycle. Following a good device address word, the second 8-bit word selects the internal register that the
control device would like to place data into. The third 8-bit word is the actual data to be placed into the selected
registers.
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