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參數(shù)資料
| 型號： | TPS2341PHPR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 4-CHANNEL POWER SUPPLY SUPPORT CKT, PQFP48 |
| 封裝： | POWERPAD, HTQFP-48 |
| 文件頁數(shù)： | 28/31頁 |
| 文件大?。?/td> | 649K |
| 代理商： | TPS2341PHPR |
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TPS2341
SLUS513A MAY 2003 REVISED JULY 2004
6
www.ti.com
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
3VAUXA
36
O
3.3Vaux voltage supply outputs. A 0.01- F bypass capacitor to PWRGND2 is recommended.
3VAUXB
35
O
3.3Vaux voltage supply outputs. A 0.01-
F bypass capacitor to PWRGND2 is recommended.
3VISA
30
I
Connect to the load side of the sense resistor. See definition for 3VS. This pin has a switched FET to
PWRGND to discharge any output load capacitance when the output is turned off. A 0.01-
F bypass
3VISB
7
I
PWRGND to discharge any output load capacitance when the output is turned off. A 0.01-
F bypass
capacitor to AGND is recommended.
3VSA
31
I
Connect to the source side of the 3.3-V FET switch. This pin in conjunction with the 3VIS pin senses
the current to the 3.3-V load by sensing the voltage drop across a sense resistor. A 0.01-
F bypass
3VSB
6
I
the current to the 3.3-V load by sensing the voltage drop across a sense resistor. A 0.01-
F bypass
capacitor to AGND is recommended.
3VSTBYIN
37
P
3.3Vaux standby voltage supply input. A 0.1-
F bypass capacitor to PWRGND2 is recommended.
5V3VGA
33
O
Gate drive for the 5-V and 3.3-V FET switches. Ramp rate is programmed by external capacitance
connected to this pin. The capacitor is charged with a 20-
A current source and discharged with a
5V3VGB
5
O
connected to this pin. The capacitor is charged with a 20-
A current source and discharged with a
switch to PWRGND. The output UV circuitry is disabled until the voltage on this pin is greater than
11 V and the voltage on P12VGx is greater than 20 V.
5VISA
29
I
Connect to the load side of the sense resistor. See definition for 5VS. 5VIS is also used to sense the
output voltage for the 5-V UV circuit. This pin has a switched FET to PWRGND to discharge any out-
5VISB
8
I
output voltage for the 5-V UV circuit. This pin has a switched FET to PWRGND to discharge any out-
put load capacitance when the output is turned off. A 0.01-
F bypass capacitor to AGND is recom-
mended.
5VSA
28
I
Connect to the source of the 5-V FET switch. This pin in conjunction with the 5VIS pin senses the
current to the 5-V load by sensing the voltage drop across the sense resistor. A 0.01-
F bypass ca-
5VSB
9
I
current to the 5-V load by sensing the voltage drop across the sense resistor. A 0.01-
F bypass ca-
pacitor to AGND is recommended.
ADDR1
17
I
Hard-wired I2C address pin. This pin represents the least significant bit (LSB) of a device’s I2C ad-
dress. Tie to DGND for a logic 0 or allow to float for a logic 1. Tie ADDR1 to DIGVCC for test mode
fault mask.
AGND
11
G
Ground pin for the internal analog section.
AUX_GOODA
27
O
Output power good indicator for the 3.3-VAUXx ouptut. This pin is driven to DIGVCC when the internal
AUX_GOODB
19
O
Output power good indicator for the 3.3-VAUXx ouptut. This pin is driven to DIGVCC when the internal
N-channel MOSFET connected between V3IN and 3VAUXA (or 3VAUXB for slot B) is fully enhanced.
DIGVCC
24
P
Power pin for the digital section, connect to 3VSTBYIN. A 0.1-
F bypass capacitor from DIGVCC to
DIGGND is recommended.
DGND
23
G
Ground pin for the internal digital section.
ENA
15
I
Hardware enable pins. Use these pins to enable the device without I2C communication. Pull ENA high
to enable slot A. Pull ENB high to enable slot B. Pull ENA low to disable slot A hardware control and
revert to I2C control. Transitioning ENA from high to low also clears the slot A main fault latch. Pull
ENB
16
I
revert to I2C control. Transitioning ENA from high to low also clears the slot A main fault latch. Pull
ENB low to disable slot B hardware control and revert to I2C control. Transitioning ENB from high to
low also clears the slot B main fault latch.
IRQ#
18
O
Interrupt output. Open drain pulls low upon any fault detection or if SWA or SWB changes state.
M12VGA
41
O
A capacitor connected from this pin to M12VOA programs the ramp rate of the 12-V switched output.
The capacitor is charged with a 20-
A current source and discharged with a switch to PWRGND.
M12VGB
48
O
A capacitor connected from this pin to M12VOB programs the ramp rate of the 12-V switched output.
The capacitor is charged with a 20-
A current source and discharged with a switch to PWRGND.
M12VIN
2
P
12-V input voltage to the device. M12VIN, M12VINA and M12VINB must be tied together and are
internally connected by a high-resistance path. The heat conduction pad on the back of the package is
M12VIN
39
P
internally connected by a high-resistance path. The heat conduction pad on the back of the package is
also connected to M12VIN. A 0.1-
F bypass capacitor from M12VIN to PWRGND is recommended.
M12VINA
40
P
12-V input voltage to the device and the 12-V power FET. M12VINA, and M12VINB and M12VIN
must be tied together and are internally connected by a high-resistance path. The heat conducting pad
M12VINB
1
P
must be tied together and are internally connected by a high-resistance path. The heat conducting pad
on the back of the package is also connected to M12VIN. A 0.1-
F bypass capacitor from M12VIN to
PWRGND is recommended.
M12VOA
38
O
12-V Switched output. This pin has a switched FET to PWRGND to discharge any output load capac-
M12VOB
3
O
12-V Switched output. This pin has a switched FET to PWRGND to discharge any output load capac-
itance when the output is turned off. A 0.01-
F bypass capacitor to PWRGND is recommended.
OCSET
10
I
A resistor connected between this pin and AGND sets the overcurrent threshold of the internal
switches. The +12-V and 12-V switches are set for the maximum permissible currents per the PCI
specification when a 1%, 6.04-k
resistor is used. A 0.1-F bypass capacitor from OCSET to
ANAGND is recommended.
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