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3.5 Configurations At Reset
3.5.1
Device and Peripheral Configurations at Device Reset
TMS320DM6437
Digital Media Processor
SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
Some device configurations are determined at reset. The following subsections give more details.
Table 2-5
, BOOT Terminal Functions lists the device boot and configuration pins that are latched at device
reset for configuring basic device settings for proper device operation.
Table 3-12
, summarizes the device
boot and configuration pins, and the device functions that they affect.
Table 3-12. Default Functions Affected by Device Boot and Configuration Pins
DEVICE BOOT AND
CONFIGURATION PINS
BOOTMODE[3:0]
BOOT SELECTED
PIN MUX CONTROL
GLOBAL SETTING
PERIPHERAL SETTING
Boot Mode
PINMUX0/PINMUX1
Registers
:
Based on
BOOTMODE[3:0], the
bootloader code programs VDD3P3V_PWDN register the PSC to put
PINMUX0 and PINMUX1
to power up the I/O pins
registers to select the
required for boot.
appropriate pin functions
required for boot.
–
Sets Device Frequency
:
Based on BOOTMODE,
FASTBOOT, PLLMS, and
AEM the bootloader code
programs PLLC1.
PINMUX0.AEAW
:
Sets Device Frequency
:
AEAW[2:0] sets the
Based on BOOTMODE,
default of this field to
FASTBOOT, PLLMS, and
control the EMIFA
AEM the bootloader code
address bus width (
only
programs PLLC1.
applicable if
PINMUX0.AEM = 001b).
I/O Pin Power
:
Based on
BOOTMODE[3:0], the
bootloader code programs bootloader code programs
PSC/Peripherals
:
Based on
BOOTMODE[3:0], the
boot-related peripheral(s)
in the Enable State, and
programs the peripheral(s)
for boot operation.
–
FASTBOOT
Fastboot
AEAW[2:0]/PLLMS[2:0]
If FASTBOOT = 1 and
AEM = 000b, 011b, 100b
or 101b the PLLMS[2:0]
selects the FASTBOOT
PLL Multiplier.
–
Affects the pin muxing in
EMIFA/VPSS Sub-Block
0.
AEM[2:0]
Together with FASTBOOT
PINMUX0.AEM
:
and PLLMS[2:0] ,
determines the
FASTBOOT PLL
Multiplier.
Sets Device Frequency
:
Based on BOOTMODE,
FASTBOOT, PLLMS, and
AEM the bootloader code
programs PLLC1.
PSC/EMIFA
:
The EMIFA module state
defaults to SwRstDisable
if AEM = 0; otherwise, the
EMIFA module state
defaults to Enable.
Sets the default of this
field to control the EMIFA
Pinout Mode.
Affects the pin muxing in
EMIFA/VPSS Sub-Block
0, 1, and 3.
PINMUX1.PCIEN
:
sets this field to control
the PCI pin muxing in
Host Block, PCI Data
Block, GPIO Block,
EMIFA/VPSS Sub-Block 0
and Sub-Block 3.
(1)(2)
PCIEN
(1)
Host Boot
:
PCIEN selects the type of
Host Boot
(HPI Boot
or
PCI Boot)
–
PSC/Peripheral
(Applicable to Host Boot
only)
:
Based on the Host Boot
type (PCI
or
HPI), the
bootloader code programs
the PSC to put the
corresponding peripheral
in the Enable State, and
programs the peripheral
for boot operation.
(1)
(2)
Software can modify all PINMUX0 and PINMUX1 bit fields from their defaults,
except
for PINMUX1.PCIEN.
In addition to pin mux control, PCIEN also affects the internal pullup/down resistors of the PCI capable pins. When PCIEN = 0, internal
pullup/down resistors on the PCI capable pins are enabled. When PCIEN = 1, internal pullup/down resistors on the PCI capable pins are
disabled to be compliant to the
PCI Local Bus Specification Revision 2.3
.
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