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P
TMS320DM6437
Digital Media Processor
SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
3.7.2.2
PINMUX1 Register Description
The Pin Multiplexing 1 Register (PINMUX1) controls the pin multiplexing of all Pin Mux Blocks. The
PINMUX1 register format is shown in
Figure 3-13
and the bit field descriptions are given in
Table 3-20
.
Some muxed pins are controlled by more than one PINMUX bit field. For the combination of PINMUX bit
fields that control each muxed pin, see
Section 3.7.3.1
,
Multiplexed Pins on DM6437
.
31
26
25
24
23
22
21
20
19
18
17
16
RESERVED
SPBK1
SPBK0
TIM1BK
RSV
TIM0BK
R/W-0000 00
R/W-00
R/W-00
R/W-00
R/W-00
R/W-00
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CKOBK
RSV
PWM1BK
UR0FCBK
RSV
UR0DBK
RSV
HOSTBK
RESERVED
PCIEN
R/W-01
R/W-0
R/W-0
R/W-00
R/W-0
R/W-0
R/W-0
R/W-000
R/W-000
R-P
LEGEND: R/W = Read/Write; R = Read only; P = specified pin state; -
n
= value after reset
(1)
For proper DM6437 device operation,
always
write a value of "0" to all RESERVED/RSV bits.
Figure 3-13. PINMUX1 Register
(1)
Table 3-20. PINMUX1 Register Bit Descriptions
Bit
Field Name
Description
Pins Controlled
Reserved. For proper device operation, the user should only write "0" to this bit
(
default
).
31:26
RESERVED
–
Serial Port Sub-Block 1 Pin Select.
Selects the function of the multiplexed pins in the Serial Port Sub-Block 1.
00 = GPIO Mode (
default
).
Pins function as GPIO (GP[110:105]).
Serial Port Sub-Block 1:
AXR0[0]/FSR1/GP[105]
ACLKX0/CLKX1/GP[106]
AFSX0/DX1/GP[107]
AHCLKX0/CLKR1/GP[108]
AMUTEIN0/FSX1/GP[109]
AMUTE0/DR1/GP[110]
01 = McBSP1 Mode.
Pins function as McBSP1: CLKX1, FSX1, DX1, CLKR1, FSR1, and DR1.
25:24
SPBK1
10 = McASP0 Transmit and 1 serializer.
Pins function as McASP0: AXR0[0], ACLKX0, AFSX0, AHCLKX0, AMUTEIN0,
and AMUTE0.
11 = McBSP1 Transmit + McASP0 SPDIF Mode.
Pins function as McBSP1 transmit (CLKX1, FSX1, DX1)
and
McASP0 SPDIF
(AXR0[0], AHCLKX0, AMUTE0).
Serial Port Sub-Block 0 Pin Select.
Selects the function of the multiplexed pins in the Serial Port Sub-Block 0.
00 = GPIO Mode (
default
).
Pins function as GPIO (GP[104:99]).
Serial Port Sub-Block 0:
ACLKR0/CLKX0/GP[99]
AFSR0/DR0/GP[100]
AHCLKR0/CLKR0/GP[101]
AXR0[3]/FSR0/GP[102]
AXR0[2]/FSX0/GP[103]
AXR0[1]/DX0/GP[104]
01 = McBSP0 Mode.
Pins function as McBSP0 CLKX0, FSX0, DX0, CLKR0, FSR0, and DR0.
23:22
SPBK0
10 = McASP0 Receive and 3 serializers.
Pins function as McASP0 ACLKR0, AFSR0, AHCLKR0, AXR0_3, AXR0_2, and
AXR0_1.
11 = Reserved
Timer1 Block Pin Select.
Selects the function of the multiplexed pins in theTimer1 Block.
00 = GPIO Mode (
default
).
Pins function as GPIO (GP[56:55]).
Timer1 Block:
HECC_RX/TINP1L/URXD1/GP[56]
HECC_TX/TOUT1L/UTXD1/GP[55]
01 = Timer1 Mode.
Pins function as Timer1 TINP1L and TOUT1L.
21:20
TIM1BK
10 = UART1 Data Mode.
Pins function as UART1 data pins URXD1 and UTXD1.
11 = HECC Mode.
Pins function as HECC HECC_RX and HECC_TX.
Device Configurations
110
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