參數(shù)資料
型號： TMS320V642AGDK6
廠商： Texas Instruments, Inc.
英文描述： 1A, 52kHz (250kHz Max) Current Mode PWM Control Circuit with 8.4V UVLO Threshold and 48% Max Duty Cycle; Package: SOIC 14 LEAD; No of Pins: 14; Container: Tape and Reel; Qty per Container: 2500
中文描述： 視頻/影像定點數(shù)字信號處理器
文件頁數(shù)： 99/123頁
文件大?。?/td> 1205K
代理商： TMS320V642AGDK6
www.ti.com
6.9
Enhanced Control Peripherals
6.9.1
Enhanced Pulse Width Modulator (ePWM) Timing
PWM
(B)
TZ
XCLKOUT
(A)
t
w(TZ)
t
d(TZ-PWM)HZ
TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
PWM refers to PWM outputs on ePWM1-6.
Table 6-20
shows the PWM timing requirements and
Table 6-21
, switching characteristics.
Table 6-20. ePWM Timing Requirements
(1)
TEST CONDITIONS
Asynchronous
Synchronous
With input qualifier
MIN
MAX
UNIT
cycles
cycles
cycles
t
w(SYCIN)
Sync input pulse width
2t
c(SCO)
2t
c(SCO)
1t
c(SCO)
+ t
w(IQSW)
(1)
For an explanation of the input qualifier parameters, see
Table 6-13
.
Table 6-21. ePWM Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
20
MAX
UNIT
ns
cycles
ns
t
w(PWM)
t
w(SYNCOUT)
t
d(PWM)tza
Pulse duration, PWMx output high/low
Sync output pulse width
Delay time, trip input active to PWM forced high
Delay time, trip input active to PWM forced low
Delay time, trip input active to PWM Hi-Z
8t
c(SCO)
no pin load
25
t
d(TZ-PWM)HZ
20
ns
6.9.2
Trip-Zone Input Timing
A.
B.
TZ - TZ1, TZ2, TZ3, TZ4, TZ5, TZ6
PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM
recovery software.
Figure 6-14. PWM Hi-Z Characteristics
Table 6-22. Trip-Zone input Timing Requirements
(1)
MIN
MAX
UNIT
cycles
cycles
cycles
t
w(TZ)
Pulse duration, TZx input low
Asynchronous
Synchronous
With input qualifier
1t
c(SCO)
2t
c(SCO)
1t
c(SCO)
+ t
w(IQSW)
(1)
For an explanation of the input qualifier parameters, see
Table 6-13
.
Electrical Specifications
99
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