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參數(shù)資料
| 型號： | TMS320LC546 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Digital Signal Processors(20/25ns指令周期， 高性能，大并行度，特殊指令集可有效實現(xiàn)多種復(fù)雜算法及應(yīng)用的DSP) |
| 中文描述： | 數(shù)字信號處理器（20/25ns指令周期，高性能，大并行度，特殊指令集可有效實現(xiàn)多種復(fù)雜算法及應(yīng)用的數(shù)字信號處理器） |
| 文件頁數(shù)： | 31/107頁 |
| 文件大小： | 2149K |
| 代理商： | TMS320LC546 |
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TMS320C54x, TMS320LC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039A – FEBRUARY 1996 – REVISED JULY 1997
28
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
serial ports
The ’C54x/’LC54x devices provide high-speed full-duplex serial ports that allow direct interface to other
’C54x/’LC54x devices, codecs, and other devices in a system. There is a standard serial port, a
time-division-multiplexed (TDM) serial port, and a buffered serial port (BSP).
The general-purpose serial port utilizes two memory-mapped registers for data transfer: the data-transmit
register (DXR) and the data-receive register (DRR). Both of these registers can be accessed in the same
manner as any other memory location. The transmit and receive sections of the serial port each have associated
clocks, frame-synchronization pulses, and serial-shift registers; and serial data can be transferred either in
bytes or in 16-bit words. Serial port receive and transmit operations can generate their own maskable transmit
and receive interrupts (XINT and RINT), allowing serial-port transfers to be managed through software. The
’C54x/’LC54x serial ports are double-buffered and fully static.
The TDM port allows the device to communicate through time-division multiplexing with up to seven other
’C54x/’LC54x devices with TDM ports. Time-division multiplexing is the division of time intervals into a number
of subintervals with each subinterval representing a prespecified communications channel. The TDM port
serially transmits 16-bit words on a single data line (TDAT) and destination addresses on a single address line
(TADD). Each device can transmit data on a single channel and receive data from one or more of the eight
channels, providing a simple and efficient interface for multiprocessing applications. A frame synchronization
pulse occurs once every 128 clock cycles, corresponding to the transmission of one 16-bit word on each of the
eight channels. Like the general-purpose serial port, the TDM port is double-buffered on both input and output
data. The TDM port can also be configured in software to operate as a general-purpose serial port as described
above. Both types of ports described above are capable of operating at up to one-fourth the machine cycle rate
(CLKOUT).
The buffered serial port (BSP) consists of a full-duplex double-buffered serial-port interface (SPI) and an
auto-buffering unit (ABU). The SPI block of the BSP is an enhanced version of the standard serial port. The ABU
allows the SPI to read/write directly to the ’C54x/’LC54x internal memory using a dedicated bus independent
of the CPU. This results in minimal overhead for SPI transactions and faster data rates.
When auto-buffering capability is disabled (standard mode), transfers with SPI are performed under software
control through interrupts. In this mode, the ABU is transparent and the word-based interrupts (WXINT and
WRINT) provided by the SPI are sent to the CPU as transmit interrupt (XINT) and receive interrupt (RINT).
When auto buffering is enabled, word transfers are done directly between the SPI and the ’C54x/’LC54x internal
memory using ABU-embedded address generators.
The ABU has its own set of circular-addressing registers with corresponding address-generation units. Memory
for the buffers resides in 2K words of the ’C54x/’LC54x internal memory. The length and starting addresses of
the buffers are user-programmable. A buffer-empty/buffer-full interrupt can be posted to the CPU. Buffering is
easily halted by an auto-disabling capability. Auto-buffering capability can be enabled separately for transmit
and receive sections. When auto buffering is disabled, operation is similar to that of the general-purpose serial
port.
The SPI allows transfer of 8-, 10-, 12-, or 16-bit data packets. In burst mode, data packets are directed by a
frame synchronization pulse for every packet. In continuous mode, the frame synchronization pulse occurs
when the data transmission is initiated and no further pulses occur. The frame and clock strobes are frequency-
and polarity-programmable. The SPI is fully static and operates at arbitrarily low clock frequencies. The
maximum operating frequency is CLKOUT (40 MBps at 25 ns).
A
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