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參數(shù)資料
| 型號(hào)： | TMS320LC546 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | Digital Signal Processors(20/25ns指令周期， 高性能，大并行度，特殊指令集可有效實(shí)現(xiàn)多種復(fù)雜算法及應(yīng)用的DSP) |
| 中文描述： | 數(shù)字信號(hào)處理器（20/25ns指令周期，高性能，大并行度，特殊指令集可有效實(shí)現(xiàn)多種復(fù)雜算法及應(yīng)用的數(shù)字信號(hào)處理器） |
| 文件頁數(shù)： | 17/107頁 |
| 文件大?。?/td> | 2149K |
| 代理商： | TMS320LC546 |
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TMS320C54x, TMS320LC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039A – FEBRUARY 1996 – REVISED JULY 1997
14
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
’C54x/’LC54x Signal Descriptions (Continued)
TERMINAL
NAME
DESCRIPTION
TYPE
OSCILLATOR/TIMER SIGNALS
CLKOUT
O/Z
Master clock output signal. CLKOUT cycles at the machine-cycle rate of the CPU. The internal machine cycle
is bounded by the rising edges of this signal. CLKOUT also goes into the high-impedance state when EMU1/OFF
is low.
CLKMD1
CLKMD2
CLKMD3
I
Clock mode external/internal input signals. CLKMD1, CLKMD2, and CLKMD3 allow you to select and configure
different clock modes, such as crystal, external clock, and various PLL factors.
X2/CLKIN
I
Input pin to internal oscillator from the crystal. If the internal (crystal) oscillator is not being used, a clock can
become input to the device using this pin. The internal machine cycle time is determined by the clock
operating-mode pins (CLKMD1, CLKMD2 and CLKMD3).
X1
O
Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left
unconnected. X1 does not go into the high-impedance state when EMU1/OFF is low.
TOUT
O/Z
Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is a CLKOUT-cycle
wide. TOUT also goes into the high-impedance state when EMU1/OFF is low.
BUFFERED SERIAL PORT 0 AND SERIAL PORT 1 SIGNALS
BCLKR0
BCLKR1
I
Receive clocks. External clock signal for clocking data from the data-receive (DR) pin into the buffered serial port
receive shift registers (RSRs). Must be present during buffered serial port transfers. If the buffered serial port is
not being used, BCLKR0 and BCLKR1 can be sampled as an input by way of IN0 bit of the SPC register.
BCLKX0
BCLKX1
I/O/Z
Transmit clock. Clock signal for clocking data from the serial port transmit shift register (XSR) to the data transmit
(DX) pin. BCLKX can be an input if MCM in the serial port control register is cleared to 0. It also can be driven
by the device at 1/(CLKDV + 1) where CLKDV range is 0–31 CLKOUT frequency when MCM is set to 1. If the
buffered serial port is not used, BCLKX can be sampled as an input by way of IN1 of the SPC register. BCLKX0
and BCLKX1 go into the high-impedance state when OFF is low.
BDR0
BDR1
I
Buffered serial-data-receive input. Serial data is received in the RSR by BDR0/BDR1.
BDX0
BDX1
O/Z
Buffered serial-port-transmit output. Serial data is transmitted from the XSR by way of BDX. BDX0 and BDX1 are
placed in the high-impedance state when not transmitting and when EMU1/OFF is low.
BFSR0
BFSR1
I
Frame synchronization pulse for receive input. The falling edge of the BFSR pulse initiates the data-receive
process, beginning the clocking of the RSR.
BFSX0
BFSX1
I/O/Z
Frame synchronization pulse for transmit input/output. The falling edge of the BFSX pulse initiates the
data-transmit process, beginning the clocking of the XSR. Following reset, the default operating condition of
BFSX is an input. BFSX0 and BFSX1 can be selected by software to be an output when TXM in the serial control
register is set to 1. This pin goes into the high-impedance state when EMU1/OFF is low.
SERIAL PORT 0 AND SERIAL PORT 1 SIGNALS
CLKR0
CLKR1
I
Receive clocks. External clock signal for clocking data from the data receive (DR) pin into the serial port receive
shift register (RSR). Must be present during serial port transfers. If the serial port is not being used, CLKR0 and
CLKR1 can be sampled as an input via IN0 bit of the SPC register.
CLKX0
CLKX1
I/O/Z
Transmit clock. Clock signal for clocking data from the serial port transmit shift register (XSR) to the data transmit
(DX) pin. CLKX can be an input if MCM in the serial port control register is cleared to 0. It also can be driven by
the device at 1/4 CLKOUT frequency when MCM is set to 1. If the serial port is not used, CLKX can be sampled
as an input via IN1 of the SPC register. CLKX0 and CLKX1 go into the high-impedance state when EMU1/OFF
is low.
DR0
DR1
I
Serial-data-receive input. Serial data is received in the RSR by DR.
DX0
DX1
O/Z
Serial port transmit output. Serial data is transmitted from the XSR via DX. DX0 and DX1 are placed in the high-im-
pedance state when not transmitting and when EMU1/OFF is low.
FSR0
FSR1
I = Input, O = Output, Z = High impedance
I
Frame synchronization pulse for receive input. The falling edge of the FSR pulse initiates the data-receive pro-
cess, beginning the clocking of the RSR.
A
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