參數(shù)資料
型號(hào): TMS320LC31-40
元件分類(lèi): 數(shù)字信號(hào)處理
英文描述: Digital Signal Processor
中文描述: 數(shù)字信號(hào)處理器
文件頁(yè)數(shù): 22/48頁(yè)
文件大?。?/td> 636K
代理商: TMS320LC31-40
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B – MARCH 1996 – REVISED JANUARY 1999
22
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
XF0 timing when executing STFI and STII
The following table defines the timing parameters for the XF0 pin during execution of STFI or STII. The number
shown in Figure 16 corresponds with the number in the NO. column of the table below.
timing parameters for XF0 when executing STFI or STII (see Figure 16)
NO.
’LC31-33
’C31-40
’LC31-40
’C31-50
’C31-60
’C31-80
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
28
td(H3H-XF0H)
Delay time, H3 high to XF0
high
15
13
12
11
8
ns
XF0 is always set high at the beginning of the execute phase of the interlock-store instruction. When no pipeline conflicts occur, the address of
the store is also driven at the beginning of the execute phase of the interlock-store instruction. However, if a pipeline conflict prevents the store
from executing, the address of the store will not be driven until the store can execute.
H3
H1
STRB
R/W
A
D
RDY
XF0 Pin
Fetch
STFI or STII
Read
Execute
28
Decode
Figure 16. Timing for XF0 When Executing an STFI or STII
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