參數(shù)資料
型號(hào): TMS320LC31-40
元件分類: 數(shù)字信號(hào)處理
英文描述: Digital Signal Processor
中文描述: 數(shù)字信號(hào)處理器
文件頁(yè)數(shù): 18/48頁(yè)
文件大?。?/td> 636K
代理商: TMS320LC31-40
T
D
S
1
P
memory read/write timing
The following table defines memory read/write timing parameters for STRB. The numbers shown in Figure 12 and Figure 13 correspond with
those in the NO. column of the table below.
timing parameters for memory (STRB = 0) read/write (see
Figure 12 and Figure 13)
NO.
’LC31-33
’C31-40
’LC31-40
’C31-50
’C31-60
’C31-80
UNIT
MIN
0
0
0
0
MAX
MIN
0
0
0
0
MAX
MIN
0
0
0
0
MAX
MIN
0
0
0
0
MAX
MIN
0
0
0
0
MAX
12
td(H1L-SL)
td(H1L-SH)
td(H1H-RWL)R
td(H1L-A)
tsu(D-H1L)R
th(H1L-D)R
tsu(RDY-H1H)
th(H1H-RDY)
td(H1H-RWH)W
tv(H1L-D)W
th(H1H-D)W
Delay time, H1 low to STRB low
10
6
5
5
5
ns
13
Delay time, H1 low to STRB high
10
6
5
5
5
ns
14
Delay time, H1 high to R/W low (read)
10
9
7
6
4
ns
15
Delay time, H1 low to A valid
14
11
9
8
7
ns
16
Setup time, D before H1 low (read)
16
14
10
9
8
ns
17
Hold time, D after H1 low (read)
0
0
0
0
0
ns
18
Setup time, RDY before H1 high
8
8
6
5
4
ns
19
Hold time, RDY after H1 high
0
0
0
0
0
ns
20
Delay time, H1 high to R/W high (write)
10
9
7
6
4
ns
21
Valid time, D after H1 low (write)
20
17
14
12
8
ns
22
Hold time, D after H1 high (write)
0
0
0
0
0
ns
23
td(H1H-A)W
Delay time, H1 high to A valid on back-to-back write
cycles (write)
18
15
12
10
8
ns
24
td(A-RDY)
Taa
Delay time, RDY from A valid
8
7
6
6
P - 8§
ns
24A
Address valid to data valid (read)
30
25
21
16
10
ns
See Figure 14 for address bus timing variation with load capacitance greater than typical load-circuit capacitance (CT = 80 pF).
This value is characterized but not tested
§In earlier data sheets, this parameter was shown as an “at speed” value. It is in fact a synchronized signal and therefore relative to Tc(H) where P = tc(C1) = tc(H)/2.
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