參數(shù)資料
型號： TMS320C6416TBGLZA8
廠商： Texas Instruments
文件頁數(shù)： 83/146頁
文件大小： 0K
描述： IC FIXED-POINT DSP 532-FCBGA
標準包裝： 60
系列： TMS320C6414T/15T/16T
類型： 定點
接口： 主機接口，McBSP，PCI，UTOPIA
時鐘速率： 850MHz
非易失內(nèi)存： 外部
芯片上RAM： 1.03MB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.20V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 532-BFBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 532-FCBGA（23x23）
包裝： 托盤
配用： 701891-ND - KIT STARTER DSP FOR C6416T
TMDXEVM6452-ND - TMDXEVM6452
296-23038-ND - DSP STARTER KIT FOR TMS320C6416
TMS320C6414T, TMS320C6415T, TMS320C6416T
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SPRS226M NOVEMBER 2003 REVISED APRIL 2009
41
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
DEVICE CONFIGURATIONS (CONTINUED)
Table 29. C6414T, C6415T, and C6416T Device Multiplexed Pins
MULTIPLEXED PINS
DEFAULT FUNCTION
DEFAULT SETTING
DESCRIPTION
NAME
NO.
DEFAULT FUNCTION
DEFAULT SETTING
DESCRIPTION
CLKOUT4/GP1
AE6
CLKOUT4
GP1EN = 0 (disabled)
These pins are software-configurable.
To use these pins as GPIO pins, the
GPxEN bits in the GPIO Enable
CLKOUT6/GP2
AD6
CLKOUT6
GP2EN = 0 (disabled)
GPxEN bits in the GPIO Enable
Register and the GPxDIR bits in the
GPIO
Direction
Register
must
be
properly configured.
CLKS2/GP8
AE4
CLKS2
GP8EN = 0 (disabled)
properly configured.
GPxEN = 1: GPx pin enabled
GPxDIR = 0: GPx pin is an input
GPxDIR = 1: GPx pin is an output
GP9/PIDSEL
M3
To use GP[15:9] as GPIO pins, the PCI
needs to be disabled (PCI_EN = 0), the
GP10/PCBE3
L2
To use GP[15:9] as GPIO pins, the PCI
needs to be disabled (PCI_EN = 0), the
GPxEN bits in the GPIO Enable
GP11/PREQ
F1
GPxEN = 0 (disabled)
GPxEN bits in the GPIO Enable
Register and the GPxDIR bits in the
GP12/PGNT
J3
None
GPxEN = 0 (disabled)
PCI_EN = 0 (disabled)
Register and the GPxDIR bits in the
GPIO
Direction
Register
must
be
properly configured.
GP13/PINTA
G4
None
PCI_EN = 0 (disabled)
GPIO
Direction
Register
must
be
properly configured.
GPxEN = 1: GPx pin enabled
GP14/PCLK
F2
GPxEN = 1: GPx pin enabled
GPxDIR = 0: GPx pin is an input
GP15/PRST
G3
GPxDIR = 0: GPx pin is an input
GPxDIR = 1: GPx pin is an output
DX1/UXADDR4
AB11
DX1
FSX1/UXADDR3
AB13
FSX1
By default, McBSP1 is enabled upon
FSR1/UXADDR2
AC9
FSR1
UTOPIA_EN (BEA11) = 0
By default, McBSP1 is enabled upon
reset (UTOPIA is disabled).
To enable the UTOPIA peripheral, an
DR1/UXADDR1
AF11
DR1
UTOPIA_EN (BEA11) = 0
(disabled)
reset (UTOPIA is disabled).
To enable the UTOPIA peripheral, an
external pullup resistor (1 k
) must be
CLKX1/URADDR4
AB12
CLKX1
(disabled)
external pullup resistor (1 k
) must be
provided on the BEA11 pin (setting
CLKS1/URADDR3
AC8
CLKS1
provided on the BEA11 pin (setting
UTOPIA_EN = 1 at reset).
CLKR1/URADDR2
AC10
CLKR1
UTOPIA_EN = 1 at reset).
CLKX2/XSP_CLK
AC2
CLKX2
DR2/XSP_DI
AB3
DR2
DX2/XSP_DO
AA2
DX2
HD[31:0]/AD[31:0]
HD[31:0]
HAS/PPAR
T3
HAS
By default, HPI is enabled upon reset
HCNTL1/PDEVSEL
R1
HCNTL1
By default, HPI is enabled upon reset
(PCI is disabled).
HCNTL0/PSTOP
T4
HCNTL0
PCI_EN = 0 (disabled)
(PCI is disabled).
To enable the PCI peripheral an external
HDS1/PSERR
T1
HDS1
PCI_EN = 0 (disabled)
To enable the PCI peripheral an external
pullup resistor (1 k
) must be provided
on the PCI_EN pin (setting PCI_EN = 1
HDS2/PCBE1
T2
HDS2
pullup resistor (1 k ) must be provided
on the PCI_EN pin (setting PCI_EN = 1
at reset).
HR/W/PCBE2
P1
HR/W
at reset).
HHWIL/PTRDY
R3
HHWIL (HPI16 only)
HINT/PFRAME
R4
HINT
HCS/PPERR
R2
HCS
HRDY/PIRDY
P4
HRDY
For the C6415T and C6416T devices, all other standalone UTOPIA and PCI pins are tied-off internally (pins in Hi-Z) when the peripheral is
disabled [UTOPIA_EN (BEA11) = 0 or PCI_EN = 0].
The C6414T device does not support the PCI and UTOPIA peripherals. These are the only multiplexed pins on the C6414T device, all other
pins are standalone peripheral functions and are not muxed.
§ For the HD[31:0]/AD[31:0] multiplexed pins pin numbers, see the Terminal Functions table.
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