參數(shù)資料
型號： TMS320C6416TBGLZA8
廠商： Texas Instruments
文件頁數(shù)： 117/146頁
文件大?。?/td> 0K
描述： IC FIXED-POINT DSP 532-FCBGA
標(biāo)準(zhǔn)包裝： 60
系列： TMS320C6414T/15T/16T
類型： 定點
接口： 主機接口，McBSP，PCI，UTOPIA
時鐘速率： 850MHz
非易失內(nèi)存： 外部
芯片上RAM： 1.03MB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.20V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 532-BFBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 532-FCBGA（23x23）
包裝： 托盤
配用： 701891-ND - KIT STARTER DSP FOR C6416T
TMDXEVM6452-ND - TMDXEVM6452
296-23038-ND - DSP STARTER KIT FOR TMS320C6416
TMS320C6414T, TMS320C6415T, TMS320C6416T
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SPRS226M NOVEMBER 2003 REVISED APRIL 2009
72
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
Table 32. Characteristics of the Power-Down Modes
PRWD FIELD
(BITS 1510)
EFFECT ON CHIP’S OPERATION
WAKE-UP METHOD
POWER-DOWN
MODE
011100
PD3
Wake by a device reset
Input clock to the PLL stops generating clocks. All register and
internal RAM contents are preserved. All functional I/O “freeze” in
the last state when the PLL clock is turned off. Following reset, the
PLL needs time to re-lock, just as it does following power-up.
Wake-up from PD3 takes longer than wake-up from PD2 because
the PLL needs to be re-locked, just as it does following power-up.
All others
Reserved
—
When entering PD2 and PD3, all functional I/O remains in the previous state. However, for peripherals which are asynchronous in nature or
peripherals with an external clock source, output signals may transition in response to stimulus on the inputs. Under these conditions,
peripherals will not operate according to specifications.
C64x power-down mode with an emulator
If user power-down modes are programmed, and an emulator is attached, the modes will be masked to allow
the emulator access to the system. This condition prevails until the emulator is reset or the cable is removed
from the header. If power measurements are to be performed when in a power-down mode, the emulator cable
should be removed.
When the DSP is in power-down mode PD2 or PD3, emulation logic will force any emulation execution
command (such as Step or Run) to spin in IDLE. For this reason, PC writes (such as loading code) will fail. A DSP
reset will be required to get the DSP out of PD2/PD3.
power-supply sequencing
TI DSPs typically do not require specific power sequencing between the core supply and the I/O supply.
However, systems should be designed to ensure that the Core is powered up prior to the I/O supply and that
the I/O supply is powered up within
≤ 200 ms of the core. This power sequence becomes even more important
in multiprocessor designs.
In addition, for proper device initialization, device reset (RESET) must be held active (low) during device power
ramp and should not be released until the PLL becomes stable.
power-supply design considerations
A dual-power supply with simultaneous sequencing can be used to eliminate the delay between core and I/O
power up. A Schottky diode can also be used to tie the core rail to the I/O rail (see Figure 11).
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