參數(shù)資料
型號(hào)： TMS320C6414TBZLZA8
廠商： Texas Instruments
文件頁數(shù)： 140/146頁
文件大?。?/td> 0K
描述： IC FIXED-POINT DSP 532-FCBGA
標(biāo)準(zhǔn)包裝： 60
系列： TMS320C6414T/15T/16T
類型： 定點(diǎn)
接口： 主機(jī)接口，McBSP，PCI，UTOPIA
時(shí)鐘速率： 850MHz
非易失內(nèi)存： 外部
芯片上RAM： 1.03MB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.20V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 532-BFBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 532-FCBGA（23x23）
包裝： 托盤
配用： TMDXEVM6452-ND - TMDXEVM6452
296-23038-ND - DSP STARTER KIT FOR TMS320C6416
TMS320C6414T, TMS320C6415T, TMS320C6416T
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SPRS226M NOVEMBER 2003 REVISED APRIL 2009
93
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
PROGRAMMABLE SYNCHRONOUS INTERFACE TIMING (CONTINUED)
ECLKOUTx
CEx
ABE[7:0] or BBE[1:0]
AEA[22:3] or BEA[20:1]
AED[63:0] or BED[15:0]
ARE/SDCAS/SADS/SRE
AOE/SDRAS/SOE
AWE/SDWE/SWE
BE1
BE2
BE3
BE4
Q1
Q2
Q3
11
3
12
10
4
2
1
8
5
8
EA1
EA2
EA3
EA4
10
Write
Latency =
1
Q4
12
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the programmable
synchronous interface access signals are shown as generic (SADS/SRE, SOE, and SWE) instead of ASADS/ASRE, ASOE, and ASWE (for
EMIFA) and BSADS/BSRE, BSOE, and BSWE (for EMIFB)].
The write latency and the length of CEx assertion are programmable via the SYNCWL and CEEXT fields, respectively, in the EMIFx CE Space
Secondary Control register (CExSEC). In this figure, SYNCWL = 1 and CEEXT = 0.
§ The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):
Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency
Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency
CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final command has been issued
(CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1).
Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with deselect cycles
(RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1).
Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2
ARE/SDCAS/SADS/SRE, AOE/SDRAS/SOE, and AWE/SDWE/SWE operate as SADS/SRE, SOE, and SWE, respectively, during
programmable synchronous interface accesses.
Figure 26. Programmable Synchronous Interface Write Timing for EMIFA and EMIFB
(With Write Latency = 1)§
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