參數(shù)資料
型號： TMS320C6414TBZLZA8
廠商： Texas Instruments
文件頁數(shù)： 124/146頁
文件大?。?/td> 0K
描述： IC FIXED-POINT DSP 532-FCBGA
標準包裝： 60
系列： TMS320C6414T/15T/16T
類型： 定點
接口： 主機接口，McBSP，PCI，UTOPIA
時鐘速率： 850MHz
非易失內(nèi)存： 外部
芯片上RAM： 1.03MB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.20V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 532-BFBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 532-FCBGA（23x23）
包裝： 托盤
配用： TMDXEVM6452-ND - TMDXEVM6452
296-23038-ND - DSP STARTER KIT FOR TMS320C6416
TMS320C6414T, TMS320C6415T, TMS320C6416T
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SPRS226M NOVEMBER 2003 REVISED APRIL 2009
79
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
PARAMETER MEASUREMENT INFORMATION (CONTINUED)
timing parameters and board routing analysis
The timing parameter values specified in this data sheet do not include delays by board routings. As a good
board design practice, such delays must always be taken into account. Timing values may be adjusted by
increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification
(IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate
timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature
number SPRA839). If needed, external logic hardware such as buffers may be used to compensate any timing
differences.
For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device and
from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time margin,
but also tends to improve the input hold time margins (see Table 33 and Figure 15).
Figure 15 represents a general transfer between the DSP and an external device. The figure also represents
board route delays and how they are perceived by the DSP and the external device.
Table 33. Board-Level Parameters Example (see Figure 15)
NO.
DESCRIPTION
1
Clock route delay
2
Minimum DSP hold time
3
Minimum DSP setup time
4
External device hold time requirement
5
External device setup time requirement
6
Control signal route delay
7
External device hold time
8
External device access time
9
DSP hold time requirement
10
DSP setup time requirement
11
Data route delay
1
2
3
4
5
6
7
8
10
11
ECLKOUTx
(Output from DSP)
ECLKOUTx
(Input to External Device)
Control Signals
(Output from DSP)
Control Signals
(Input to External Device)
Data Signals
(Output from External Device)
Data Signals
(Input to DSP)
9
Control signals include data for Writes.
Data signals are generated during Reads from an external device.
Figure 15. Board-Level Input/Output Timings
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