參數(shù)資料
型號： TMS320C6414TBZLZA7
廠商： Texas Instruments
文件頁數(shù)： 135/146頁
文件大小： 0K
描述： IC FIXED-POINT DSP 532-FCBGA
標(biāo)準(zhǔn)包裝： 60
系列： TMS320C6414T/15T/16T
類型： 定點(diǎn)
接口： 主機(jī)接口，McBSP，PCI，UTOPIA
時(shí)鐘速率： 720MHz
非易失內(nèi)存： 外部
芯片上RAM： 1.03MB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.20V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 532-BFBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 532-FCBGA（23x23）
包裝： 托盤
配用： TMDXEVM6452-ND - TMDXEVM6452
296-23038-ND - DSP STARTER KIT FOR TMS320C6416
TMS320C6414T, TMS320C6415T, TMS320C6416T
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SPRS226M NOVEMBER 2003 REVISED APRIL 2009
89
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
PROGRAMMABLE SYNCHRONOUS INTERFACE TIMING
timing requirements for programmable synchronous interface cycles for EMIFA module
(see Figure 24)
NO.
600
720
850
1G
UNIT
MIN
MAX
6
tsu(EDV-EKOxH)
Setup time, read EDx valid before ECLKOUTx high
2
ns
7
th(EKOxH-EDV)
Hold time, read EDx valid after ECLKOUTx high
1.5
ns
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the programmable
synchronous interface access signals are shown as generic (SADS/SRE, SOE, and SWE) instead of ASADS/ASRE, ASOE, and ASWE (for
EMIFA) and BSADS/BSRE, BSOE, and BSWE (for EMIFB)].
switching
characteristics
over
recommended
operating
conditions
for
programmable
synchronous interface cycles for EMIFA module (see Figure 24Figure 26)
NO.
PARAMETER
600
720
850
1G
UNIT
MIN
MAX
1
td(EKOxH-CEV)
Delay time, ECLKOUTx high to CEx valid
1.3
4.9
ns
2
td(EKOxH-BEV)
Delay time, ECLKOUTx high to BEx valid
4.9
ns
3
td(EKOxH-BEIV)
Delay time, ECLKOUTx high to BEx invalid
1.3
ns
4
td(EKOxH-EAV)
Delay time, ECLKOUTx high to EAx valid
4.9
ns
5
td(EKOxH-EAIV)
Delay time, ECLKOUTx high to EAx invalid
1.3
ns
8
td(EKOxH-ADSV)
Delay time, ECLKOUTx high to SADS/SRE valid
1.3
4.9
ns
9
td(EKOxH-OEV)
Delay time, ECLKOUTx high to, SOE valid
1.3
4.9
ns
10
td(EKOxH-EDV)
Delay time, ECLKOUTx high to EDx valid
4.9
ns
11
td(EKOxH-EDIV)
Delay time, ECLKOUTx high to EDx invalid
1.3
ns
12
td(EKOxH-WEV)
Delay time, ECLKOUTx high to SWE valid
1.3
4.9
ns
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the programmable
synchronous interface access signals are shown as generic (SADS/SRE, SOE, and SWE) instead of ASADS/ASRE, ASOE, and ASWE (for
EMIFA) and BSADS/BSRE, BSOE, and BSWE (for EMIFB)].
The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):
Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency
Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency
CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final command has been issued
(CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1).
Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with deselect cycles
(RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1).
Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2
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