參數(shù)資料
型號: TMS320C6414TBZLZA7
廠商: Texas Instruments
文件頁數(shù): 112/146頁
文件大?。?/td> 0K
描述: IC FIXED-POINT DSP 532-FCBGA
標(biāo)準(zhǔn)包裝: 60
系列: TMS320C6414T/15T/16T
類型: 定點(diǎn)
接口: 主機(jī)接口,McBSP,PCI,UTOPIA
時鐘速率: 720MHz
非易失內(nèi)存: 外部
芯片上RAM: 1.03MB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.20V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 532-BFBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 532-FCBGA(23x23)
包裝: 托盤
配用: TMDXEVM6452-ND - TMDXEVM6452
296-23038-ND - DSP STARTER KIT FOR TMS320C6416
TMS320C6414T, TMS320C6415T, TMS320C6416T
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SPRS226M NOVEMBER 2003 REVISED APRIL 2009
68
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
clock PLL (continued)
Table 31. TMS320C64x PLL Multiply Factor Options, Clock Frequency Ranges, and Typical Lock Time
GLZ, ZLZ and CLZ PACKAGES 23 x 23 mm BGA
CLKMODE1
CLKMODE0
CLKMODE
(PLL MULTIPLY
FACTORS)
CLKIN
RANGE
(MHz)
CPU CLOCK
FREQUENCY
RANGE (MHz)
CLKOUT4
RANGE (MHz)
CLKOUT6
RANGE (MHz)
TYPICAL
LOCK TIME
(
s)§
0
Bypass (x1)
0100
025
016.6
N/A
0
1
x6
4275
252450
63112.5
4275
1
0
x12
4275
504900
126225
84150
75
1
x20
2550
5001000
125250
83.3166.6
75
These clock frequency range values are applicable to a C64x600, 720, 850, and 1000-MHz speed devices. For more detailed information,
see the CLKIN timing requirements table for the specific device speed.
Use external pullup resistors on the CLKMODE pins (CLKMODE1 and CLKMODE0) to set the C64x device to one of the valid PLL multiply clock
modes (x6, x12, or x20). With internal pulldown resistors on the CLKMODE pins (CLKMODE1, CLKMODE0), the default clock mode is
x1 (bypass).
§ Under some operating conditions, the maximum PLL lock time may vary by as much as 150% from the specified typical value. For example, if
the typical lock time is specified as 100
s, the maximum value may be as long as 250 s.
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