參數(shù)資料
型號(hào)： TMS320C6414TBZLZA7
廠商： Texas Instruments
文件頁數(shù)： 116/146頁
文件大?。?/td> 0K
描述： IC FIXED-POINT DSP 532-FCBGA
標(biāo)準(zhǔn)包裝： 60
系列： TMS320C6414T/15T/16T
類型： 定點(diǎn)
接口： 主機(jī)接口，McBSP，PCI，UTOPIA
時(shí)鐘速率： 720MHz
非易失內(nèi)存： 外部
芯片上RAM： 1.03MB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.20V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 532-BFBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 532-FCBGA（23x23）
包裝： 托盤
配用： TMDXEVM6452-ND - TMDXEVM6452
296-23038-ND - DSP STARTER KIT FOR TMS320C6416
TMS320C6414T, TMS320C6415T, TMS320C6416T
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SPRS226M NOVEMBER 2003 REVISED APRIL 2009
71
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
31
16
15
14
13
12
11
10
9
8
Reserved
Enable or
Non-Enabled
Interrupt Wake
Enabled
Interrupt Wake
PD3
PD2
PD1
R/W-0
7
0
Legend: R/Wx = Read/write reset value
NOTE: The shadowed bits are not part of the power-down logic discussion and therefore are not covered here. For information on these other
bit fields in the CSR register, see the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189).
Figure 10. PWRD Field of the CSR Register
A delay of up to nine clock cycles may occur after the instruction that sets the PWRD bits in the CSR before the
PD mode takes effect. As best practice, NOPs should be padded after the PWRD bits are set in the CSR to account
for this delay.
If PD1 mode is terminated by a non-enabled interrupt, the program execution returns to the instruction where
PD1 took effect. If PD1 mode is terminated by an enabled interrupt, the interrupt service routine will be executed
first, then the program execution returns to the instruction where PD1 took effect. In the case with an enabled
interrupt, the GIE bit in the CSR and the NMIE bit in the interrupt enable register (IER) must also be set in order
for the interrupt service routine to execute; otherwise, execution returns to the instruction where PD1 took effect
upon PD1 mode termination by an enabled interrupt.
PD2 and PD3 modes can only be aborted by device reset. Table 32 summarizes all the power-down modes.
Table 32. Characteristics of the Power-Down Modes
PRWD FIELD
(BITS 1510)
POWER-DOWN
MODE
WAKE-UP METHOD
EFFECT ON CHIP’S OPERATION
000000
No power-down
—
001001
PD1
Wake by an enabled interrupt
CPU halted (except for the interrupt logic)
Power-down mode blocks the internal clock inputs at the
010001
PD1
Wake by an enabled or
non-enabled interrupt
Power-down mode blocks the internal clock inputs at the
boundary of the CPU, preventing most of the CPU’s logic from
switching. During PD1, EDMA transactions can proceed
between peripherals and internal memory.
011010
PD2
Wake by a device reset
Output clock from PLL is halted, stopping the internal clock
structure from switching and resulting in the entire chip being
halted. All register and internal RAM contents are preserved. All
functional I/O “freeze” in the last state when the PLL clock is
turned off.
When entering PD2 and PD3, all functional I/O remains in the previous state. However, for peripherals which are asynchronous in nature or
peripherals with an external clock source, output signals may transition in response to stimulus on the inputs. Under these conditions,
peripherals will not operate according to specifications.
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