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| 型號： | TMS320C44PDB-60 |
| 英文描述： | DSP|32-BIT|CMOS|QFP|304PIN|PLASTIC |
| 中文描述： | 數(shù)字信號處理器| 32位|的CMOS | QFP封裝| 304PIN |塑料 |
| 文件頁數(shù)： | 19/132頁 |
| 文件大?。?/td> | 1707K |
| 代理商： | TMS320C44PDB-60 |
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SPRS145G
–
JULY 2000
–
REVISED FEBRUARY 2002
19
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
pin functions (continued)
Table 2. LF240xA and LC240xA Pin List and Package Options
(Continued)
PIN NAME
LF2407A
(144-PGE)
2406A
(100-PZ)
LC2404A
(100-PZ)
2403A,
LC2402A
(64-PAG)
and
2402A
(64-PG)
DESCRIPTION
OSCILLATOR, PLL, FLASH, BOOT, AND MISCELLANEOUS (CONTINUED)
BIO
/IOPC1
119
85
85
Branch control input. BIO is polled by the
BCND pma,BIO
instruction. If BIO is low, a branch is executed. If BIO is not used,
it should be pulled high. This pin is configured as a branch
control input by all device resets. It can be used as a GPIO, if
not used as a branch control input.
(
↑
)
EMULATION AND TEST
EMU0
90
61
61
7
Emulator I/O #0 with internal pullup. When TRST is driven high,
this pin is used as an interrupt to or from the emulator system
and is defined as input/output through the JTAG scan.
(
↑
)
EMU1/OFF
91
62
62
8
Emulator pin 1. Emulator pin 1 disables all outputs. When TRST
is driven high, EMU1/OFF is used as an interrupt to or from the
emulator system and is defined as an input/output through the
JTAG scan. When TRST is driven low, this pin is configured as
OFF. EMU1/OFF, when active low, puts all output drivers in the
high-impedance state. Note that OFF is used exclusively for
testing and emulation purposes (not for multiprocessing
applications). Therefore, for the OFF condition, the following
apply:
TRST = 0
EMU0 = 1
EMU1/OFF = 0
(
↑
)
JTAG test clock with internal pullup
TCK
135
94
94
29
(
↑
)
TDI
139
96
96
30
JTAG test data input (TDI) with internal pullup. TDI is clocked
into the selected register (instruction or data) on a rising edge
of TCK.
(
↑
)
JTAG scan out, test data output (TDO). The contents of the
selected register (instruction or data) is shifted out of TDO on
the falling edge of TCK.
(
↓
)
JTAG test-mode select (TMS) with internal pullup. This serial
control input is clocked into the TAP controller on the rising edge
of TCK.
(
↑
)
JTAG test-mode select 2 (TMS2) with internal pullup. This serial
control input is clocked into the TAP controller on the rising edge
of TCK. Used for test and emulation only. This pin can be left
unconnected in user applications. If the PLL bypass mode is
desired, TMS2, TMS, and TRST should be held low during
reset.
(
↑
)
TDO
142
99
99
31
TMS
144
100
100
32
TMS2
36
25
25
48
Bold, italicized pin names
indicate pin function after reset.
GPIO
–
General-purpose input/output pin. All GPIOs come up as input after reset.
§
It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy
and improve the noise immunity of the ADC.
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
#No power supply pin (VDD, VDDO, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately for proper
device operation.
LEGEND:
↑
–
Internal pullup
↓
–
Internal pulldown
(Typical active pullup/pulldown value is
±
16
μ
A.)
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