參數(shù)資料
型號： TMS320C44PDB-60
英文描述： DSP|32-BIT|CMOS|QFP|304PIN|PLASTIC
中文描述： 數(shù)字信號處理器| 32位|的CMOS | QFP封裝| 304PIN |塑料
文件頁數(shù)： 10/132頁
文件大?。?/td> 1707K
代理商： TMS320C44PDB-60
SPRS145G
–
JULY 2000
–
REVISED FEBRUARY 2002
10
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
functional block diagram of the 2407A DSP controller
XTAL1/CLKIN
XTAL2
ADCIN00
–
ADCIN07
PLLVCCA
PLLF2
PLLF
VSSA
VREFHI
VREFLO
ADCIN08
–
ADCIN15
VCCA
SCIRXD/IOPA1
SPISIMO/IOPC2
SPISOMI/IOPC3
XINT2/ADCSOC/IOPD0
SCITXD/IOPA0
Port A(0
–
7) IOPA[0:7]
Port B(0
–
7) IOPB[0:7]
SPICLK/IOPC4
SPISTE/IOPC5
Port E(0
–
7) IOPE[0:7]
Port F(0
–
6) IOPF[0:6]
TRST
Port C(0
–
7) IOPC[0:7]
Port D(0) IOPD[0]
TDO
TDI
TMS
CANRX/IOPC7
CANTX/IOPC6
EMU1
PDPINTB
CAP4/QEP3/IOPE7
TCK
EMU0
CAP5/QEP4/IOPF0
CAP6/IOPF1
PWM7/IOPE1
PWM8/IOPE2
PWM9/IOPE3
PWM10/IOPE4
PWM11/IOPE5
PWM12/IOPE6
T3PWM/T3CMP/IOPF2
T4PWM/T4CMP/IOPF3
TDIRB/IOPF4
TCLKINB/IOPF5
DARAM (B0)
256 Words
DARAM (B1)
256 Words
DARAM (B2)
32 Words
C2xx
DSP
Core
PLL Clock
10-Bit ADC
(With Twin
Autosequencer)
èèèèèèè
èèèèèèè
èèèèèèè
èèèèèèè
èèèèèèè
èèèèèèè
èèèèèèèèèèèèè
èèèèèèè
èèèèèèè
èèèèèèè
èèèèèèè
èèèèèèè
èèèèèèè
èèèèèèè
èèèèèèè
èèèèèèè
RS
CLKOUT/IOPE0
XINT1/IOPA2
BIO/IOPC1
MP/MC
BOOT_EN/XF
VDD (3.3 V)
TMS2
A0
–
A15
D0
–
D15
PS, DS, IS
TP1
TP2
READY
STRB
R/W
RD
VIS_OE
ENA_144
WE
CAP3/IOPA5
PWM1/IOPA6
PWM2/IOPA7
CAP1/QEP1/IOPA3
CAP2/QEP2/IOPA4
PDPINTA
PWM5/IOPB2
PWM6/IOPB3
PWM3/IOPB0
PWM4/IOPB1
T2PWM/T2CMP/IOPB5
T1PWM/T1CMP/IOPB4
TCLKINA/IOPB7
TDIRA/IOPB6
VSS
VCCP(5V)
èèèèèèè
èèèèèèèèèèèèè
èèèèèèèèèèèèè
èèèèèèèèèèèèè
èèèèèèèèèèèèè
èèèèèèèèèèèèè
èèèèèèè
èèèèèèè
Flash/ROM
4K/12K/12K/4K)
External Memory
Event Manager A
3
×
Capture Input
6
×
Compare/PWM
Output
2
×
GP
Timers/PWM
SCI
Digital I/O
(Shared With
Other Pins)
CAN
JTAG Port
Event Manager B
3
×
Capture Input
Output
èèè
èèè
èèè
Indicates optional modules
.
The memory size and peripheral selection of these modules change for different 240xA devices.
See Table 1 for device-specific details.
W/R / IOPC0
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