
SPRS145G
–
JULY 2000
–
REVISED FEBRUARY 2002
3
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
REVISION HISTORY
REVISION
DATE
PRODUCT STATUS
HIGHLIGHTS
B
November 2000
Advance Information
The on-chip ROM size for the LC2402A device has been changed
to 6K words.
The description for the VCCP pin has been modified. This informa-
tion can be found in Table 2, LF240xA and LC240xA Pin List and
Package Options.
The conditions for high-impedance state for the strobe signals have
been changed. This information can be found in Table 2, LF240xA
and LC240xA Pin List and Package Options.
All 240xA parts will be rated for a maximum clock speed of 40 MHz.
There will be no 30-MHz 240xA parts.
The tw(CAP), tw(PDP), tw(INT), and tw(PDP-WAKE) parameters have
been changed.
Ready-on-Read and Ready-on-Write timings for one software wait
state and one external wait state have been added.
Bits 15 and 8 of the SCSR1 register are now reserved (see
Table 19, LF240xA/LC240xA DSP Peripheral Register Description).
A new section, Migrating From 240x Devices to 240xA Devices, has
been added.
The boot ROM description has changed. It can now support the x2
or x4 option for the PLL, depending on the state of the SCITXD pin.
C
(Internal
Revision)
February 2001
Advance Information
Added LF2403A device
Added 64-pin PAG thin quad flatpack (TQFP)
The th(A)COLW parameter is now referenced from the next falling
CLKOUT edge than what was shown in the previous data sheets.
The specification for this parameter is
–
5 ns (MIN).
D
March 2001
Advance Information
VCCP is a No Connect (NC) on the ROM devices (LC240xA).
Addresses 8800h
–
FDFFh in LC2406A and LC2402A are Reserved
(see Figure 5 and Figure 7, respectively).
Addresses 8400h
–
FDFFh in LC2404A are Reserved (see Figure 6).
Table 15, Development Support Tools, has been updated.
Table 16, TMS320x24x-Specific Development Tools, has been
updated.
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