
SPRS145G
–
JULY 2000
–
REVISED FEBRUARY 2002
23
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
pin functions (continued)
Table 2. LF240xA and LC240xA Pin List and Package Options
(Continued)
PIN NAME
LF2407A
(144-PGE)
2406A
(100-PZ)
LC2404A
(100-PZ)
2403A,
LC2402A
(64-PAG)
and
2402A
(64-PG)
DESCRIPTION
ADDRESS, DATA, AND MEMORY CONTROL SIGNALS (CONTINUED)
D6
143
Bit 6 of 16-bit data bus
(
↑
)
(
↑
)
(
↑
)
(
↑
)
(
↑
)
(
↑
)
(
↑
)
(
↑
)
(
↑
)
(
↑
)
D7
5
Bit 7 of 16-bit data bus
D8
9
Bit 8 of 16-bit data bus
D9
13
Bit 9 of 16-bit data bus
D10
15
Bit 10 of 16-bit data bus
D11
17
Bit 11 of 16-bit data bus
D12
20
Bit 12 of 16-bit data bus
D13
22
Bit 13 of 16-bit data bus
D14
24
Bit 14 of 16-bit data bus
D15
27
Bit 15 of 16-bit data bus
POWER SUPPLY
6
29
20
20
VDD#
50
35
35
27
Core supply 3 3 V Digital logic supply voltage
Core supply +3.3 V. Digital logic supply voltage.
86
59
59
56
129
91
91
4
4
4
10
42
30
30
35
VDDO#
67
47
47
52
I/O buffer supply +3.3 V. Digital logic and buffer supply
voltage.
77
54
54
95
64
64
141
98
98
28
19
19
5
VSS#
49
34
34
26
Core ground Digital logic ground reference
Core ground. Digital logic ground reference.
85
58
58
55
128
90
90
3
3
3
9
41
29
29
34
66
46
46
51
VSSO#
76
53
53
I/O buffer ground. Digital logic and buffer ground reference.
94
63
63
125
140
97
97
Bold, italicized pin names
indicate pin function after reset.
GPIO
–
General-purpose input/output pin. All GPIOs come up as input after reset.
§
It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy
and improve the noise immunity of the ADC.
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
#No power supply pin (VDD, VDDO, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately for proper
device operation.
LEGEND:
↑
–
Internal pullup
↓
–
Internal pulldown
(Typical active pullup/pulldown value is
±
16
μ
A.)