參數(shù)資料
型號： TMS320C2812ZHHS
廠商： TEXAS INSTRUMENTS INC
元件分類： 數(shù)字信號處理
英文描述： 16-BIT, 150 MHz, OTHER DSP, PBGA179
封裝： LEAD FREE, BGA-179
文件頁數(shù)： 151/156頁
文件大小： 1826K
代理商： TMS320C2812ZHHS
Electrical Specifications
94
April 2001 Revised October 2005
SPRS174M
6.4
Current Consumption by Power-Supply Pins Over Recommended Operating Conditions
During Low-Power Modes at 150-MHz SYSCLKOUT (TMS320F281x)
MODE
TEST CONDITIONS
IDD
IDDIO
IDD3VFL
IDDA
MODE
TEST CONDITIONS
TYP
MAX§
TYP
MAX§
TYP
MAX§
TYP
MAX§
Operational
All peripheral clocks are enabled. All
PWM pins are toggled at 100 kHz.
Data is continuously transmitted out of
the SCIA, SCIB, and CAN ports. The
hardware multiplier is exercised.
Code is running out of flash with 5
wait-states.
195 mA
230 mA
15 mA
30 mA
40 mA
45 mA
40 mA
50 mA
IDLE
Flash is powered down
XCLKOUT is turned off
All peripheral clocks are on,
except ADC
125 mA
150 mA
5 mA
10 mA
2
A
4
A
1
A
20
A
STANDBY
Flash is powered down
Peripheral clocks are turned off
Pins without an internal PU/PD
are tied high/low
5 mA
10 mA
5
A
20
A
2
A
4
A
1
A
20
A
HALT
Flash is powered down
Peripheral clocks are turned off
Pins without an internal PU/PD
are tied high/low
Input clock is disabled
70
A
5
A
20
A
2
A
4
A
1
A
20
A
IDDIO current is dependent on the electrical loading on the I/O pins.
IDDA includes current into VDDA1, VDDA2, AVDDREFBG, and VDDAIO pins.
§ MAX numbers are at 125°C, and MAX voltage (VDD = 2.0 V; VDDIO, VDD3VFL, VDDA = 3.6 V).
IDD represents the total current drawn from the 1.8-V rail (VDD). It includes a small amount of current (<1 mA) drawn by VDD1.
NOTE:
HALT and STANDBY modes cannot be used when the PLL is disabled.
6.5
Current Consumption by Power-Supply Pins Over Recommended Operating Conditions
During Low-Power Modes at 150-MHz SYSCLKOUT (TMS320C281x)
MODE
TEST CONDITIONS
IDD
IDDIO
IDDA
MODE
TEST CONDITIONS
TYP
MAX§
TYP
MAX§
TYP
MAX§
Operational
All peripheral clocks are enabled. All PWM pins are
toggled at 100 kHz.
Data is continuously transmitted out of the SCIA, SCIB,
and CAN ports. The hardware multiplier is exercised.
Code is running out of ROM with 5 wait-states.
210 mA
260 mA
20 mA
30 mA
40 mA
50 mA
IDLE
XCLKOUT is turned off
All peripheral clocks are on, except ADC
140 mA
155 mA
20 mA
30 mA
5
A
10
A
STANDBY
Peripheral clocks are turned off
Pins without an internal PU/PD are tied high/low
5 mA
10mA
5
A
20
A
5
A
10
A
HALT
Peripheral clocks are turned off
Pins without an internal PU/PD are tied high/low
Input clock is disabled
70
A
5
A
10
A
1
A
IDDIO current is dependent on the electrical loading on the I/O pins.
IDDA includes current into VDDA1, VDDA2, AVDDREFBG, and VDDAIO pins.
§ MAX numbers are at 125°C, and MAX voltage (VDD = 2.0 V; VDDIO, VDD3VFL, VDDA = 3.6 V).
IDD represents the total current drawn from the 1.8-V rail (VDD). It includes a small amount of current (<1 mA) drawn by VDD1.
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