參數(shù)資料
型號(hào)： TMS320C2812ZHHS
廠商： TEXAS INSTRUMENTS INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 16-BIT, 150 MHz, OTHER DSP, PBGA179
封裝： LEAD FREE, BGA-179
文件頁數(shù)： 15/156頁
文件大?。?/td> 1826K
代理商： TMS320C2812ZHHS
Electrical Specifications
111
April 2001 Revised October 2005
SPRS174M
6.17
Event Manager Interface
6.17.1
PWM Timing
PWM refers to all PWM outputs on EVA and EVB.
Table 616. PWM Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
tw(PWM)§
Pulse duration, PWMx output high/low
25
ns
td(PWM)XCO
Delay time, XCLKOUT high to PWMx output switching
XCLKOUT = SYSCLKOUT/4
10
ns
See the GPIO output timing for fall/rise times for PWM pins.
PWM pin toggling frequency is limited by the GPIO output buffer switching frequency (20 MHz).
§ PWM outputs may be 100%, 0%, or increments of tc(HCO) with respect to the PWM period.
Table 617. Timer and Capture Unit Timing Requirements#
MIN
MAX
UNIT
tw(TDIR)
Pulse duration, TDIRx low/high
Without input qualifier
2tc(SCO)
cycles
tw(TDIR)
Pulse duration, TDIRx low/high
With input qualifier
1tc(SCO) + IQT||
cycles
tw(CAP)
Pulse duration, CAPx input low/high
Without input qualifier
2tc(SCO)
cycles
tw(CAP)
Pulse duration, CAPx input low/high
With input qualifier
1tc(SCO) + IQT||
cycles
tw(TCLKINL)
Pulse duration, TCLKINx low as a percentage of TCLKINx cycle time
40
60
%
tw(TCLKINH)
Pulse duration, TCLKINx high as a percentage of TCLKINx cycle time
40
60
%
tc(TCLKIN)
Cycle time, TCLKINx
4tc(HCO)
ns
The QUALPRD bit field value can range from 0 (no qualification) through 0xFF (510 SYSCLKOUT cycles). The qualification sampling period is
2n SYSCLKOUT cycles, where “n” is the value stored in the QUALPRD bit field. As an example, when QUALPRD = 1, the qualification sampling
period is 1 x 2 = 2 SYSCLKOUT cycles (i.e., the input is sampled every 2 SYSCLKOUT cycles). Six such samples will be taken over five sampling
windows, each window being 2n SYSCLKOUT cycles. For QUALPRD = 1, the minimum width that is needed is 5 x 2 = 10 SYSCLKOUT cycles.
However, since the external signal is driven asynchronously, a 11-SYSCLKOUT-wide pulse ensures reliable recognition.
# Maximum input frequency to the QEP = min[HSPCLK/2, 20 MHz]
|| Input Qualification Time (IQT) = [tc(SCO) 2 QUALPRD] 5 + [tc(SCO) 2 QUALPRD].
tw(PWM)
td(PWM)XCO
PWMx
XCLKOUT
XCLKOUT = SYSCLKOUT
Figure 617. PWM Output Timing
XCLKOUT
tw(TDIR)
TDIRx
XCLKOUT = SYSCLKOUT
Figure 618. TDIRx Timing
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