
SPRS145G
–
JULY 2000
–
REVISED FEBRUARY 2002
6
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
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1443
REVISION HISTORY (CONTINUED)
REVISION
DATE
PRODUCT STATUS
HIGHLIGHTS
F
(continued)
October 2001
Production Data
In the Current Consumption by Power-Supply Pins Over
Recommended Operating Free-Air Temperature Ranges During
Low-Power Modes at 40-MHz CLOCKOUT tables for the
TMS320LC2406A, TMS320LC2404A, and the TMS320LC2402A:
–
Updated TYP and MAX IDD values for LPM1
–
Updated the LPM2 test conditions
–
Added footnote about clock source
Updated Figure 20, LF2407A Typical Current Consumption (With
Peripheral Clocks Enabled).
Updated the MIN tc(CO) value in the Switching Characteristics Over
Recommended Operating Conditions table in the External
Reference Crystal/Clock With PLL Circuit Enabled section.
Updated the Switching Characteristics tables and the Timing
Requirements Tables in the External Memory Interface section.
Added the ADC Operating Frequency (LF240xA) table.
Added a Zero-Offset Error specification to the Operating
Characteristics Over Recommended Operating Condition Ranges
table in the 10-Bit Analog-to-Digital Converter (ADC) section.
Added: EDNL and EINL for LF2407A/LF2406A/LF2403A/LF2402A
table.
Updated the tc(AD) and tw(SHC) parameters in the Internal ADC Mod-
ule Timings table.
Added footnote about Flash algorithm upgrades to the Flash
Parameters @40 MHz CLOCKOUT table.
Updated the ADCCTRL1 (0x070A0), ADCCTRL2 (0x070A1), and
PDDATDIR (0x0709E) registers in Table 19, LF240xA/LC240xA
DSP Peripheral Register Description.
Address location 0x070B8, formerly occupied by the Calibration
register, is now Reserved. (See Table 19, LF240xA/LC240xA DSP
Peripheral Register Description.)