
SPRS145G
–
JULY 2000
–
REVISED FEBRUARY 2002
109
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
10-bit analog-to-digital converter (ADC)
The 10-bit ADC has a separate power bus for its analog circuitry. These pins are referred to as V
CCA
and V
SSA
.
The power bus isolation is to enhance ADC performance by preventing digital switching noise of the logic
circuitry that can be present on V
SS
and V
CC
from coupling into the ADC analog stage. All ADC specifications
are given with respect to V
SSA
unless otherwise noted.
Resolution
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monotonic
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output conversion mode
000h to 3FFh (000h for V
I
≤
V
REFLO
; 3FFh for V
I
≥
V
REFHI
)
. . . . . . . . . . . . . . . . . . .
Minimum conversion time (including sample time)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-bit (1024 values)
Assured
375 ns
recommended operating conditions
MIN
NOM
MAX
UNIT
VCCA
VSSA
VREFHI
VREFLO
VAI
VREFHI and VREFLO must be stable, within
±
1/2 LSB of the required resolution, during the entire conversion time.
Analog supply voltage
3.0
3.3
3.6
V
Analog ground
Analog supply reference source
Analog ground reference source
0
V
VREFLO
VSSA
VREFLO
VCCA
VREFHI
VREFHI
V
V
Analog input voltage, ADCIN00
–
ADCIN07
V
ADC operating frequency (LF240xA)
MIN
MAX
30
UNIT
MHz
ADC operating frequency
4
ADC operating frequency (LC240xA)
MIN
MAX
40
UNIT
MHz
ADC operating frequency
4