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| 型號： | TMPR28051 |
| 英文描述： | TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 5 of the Device |
| 中文描述： | TMPR28051 STS-1/AU-3（的STM - 0）映射為版本的設(shè)備5設(shè)備咨詢 |
| 文件頁數(shù)： | 74/90頁 |
| 文件大?。?/td> | 1090K |
| 代理商： | TMPR28051 |
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Data Sheet
August 1999
TMPR28051 STS-1/AU-3 (STM-0) Mapper
60
Lucent Technologies Inc.
Microprocessor Interface Description
(continued)
I/O Timing
The I/O timing specifications for the microprocessor interface are given in Table 33. The microprocessor interface
pins use CMOS I/O levels (see pages 20—22 for pin listings). All outputs, except the address/data bus AD[7:0], are
rated for a capacitive load of 50 pF. The AD[7:0] outputs are rated for a 100 pF load. The minimum read and write
cycle time is 200 ns for all device configurations.
The read and write timing diagrams for all four microprocessor interface modes are shown in Figures 3—10.
Table 33. Microprocessor Interface I/O Timing Specifications
Symbol
Configuration
Parameter
Setup
(ns)
(Min)
5
—
0
25
—
—
—
—
—
—
—
—
7
20
7.5
—
—
—
15
—
30
—
—
—
—
35
—
25
—
—
—
—
—
—
Hold
(ns)
(Min)
—
10
—
—
—
—
—
—
—
—
75
35
—
—
—
—
7.5
35
—
10
—
—
—
—
—
—
—
—
—
—
25
150
100
100
Delay
(ns)
(Max)
—
—
—
—
20
24
44
—
15
15
—
—
—
—
—
20
—
—
—
—
—
90
75
25
25
—
16
—
73
22
—
—
—
—
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
t23
t24
t25
t26
t27
t28
t29
t30
t31
t32
t33
t34
Modes 1 & 2
Address Valid to AS Asserted (Read, Write)
AS Asserted to Address Invalid (Read, Write)
AS Asserted to DS Asserted
R/W High (Read) to DS Asserted
DS Asserted (Read, Write) to DTACK Asserted
DTACK Asserted to Data Valid (Read)
DS Asserted (Read) to Data Valid
DS Negated (Read, Write) to AS Negated
DS Negated (Read) to Data Invalid
DS Negated (Read) to DTACK Negated
AS (Read, Write) Asserted Width
DS (Read) Asserted Width
AS Asserted to R/W Low (Write)
R/W Low (Write) to DS Asserted
Data Valid to DS Asserted (Write)
DS Negated to DTACK Negated (Write)
DS Negated to Data Invalid (Write)
DS (Write) Asserted Width
Address Valid to ALE Asserted Low (Read, Write)
ALE Asserted Low (Read, Write) to Address Invalid
ALE Asserted Low to RD Asserted (Read)
RD Asserted (Read) to Data Valid
RD Asserted (Read) to RDY Asserted
RD Negated to Data Invalid (Read)
RD Negated to RDY Negated (Read)
ALE Asserted Low to WR Asserted (Write)
CS Asserted to RDY Asserted Low
Data Valid to WR Asserted (Write)
WR Asserted (Write) to RDY Asserted
WR Negated to RDY Negated (Write)
WR Negated to Data Invalid
ALE Asserted (Read, Write) Width
RD Asserted (Read) Width
WR Asserted (Write) Width
Modes 3 & 4
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