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參數(shù)資料
| 型號： | TMP93C071F |
| 廠商： | Toshiba Corporation |
| 元件分類： | 微控制器 |
| 英文描述： | Quality And Reliability Assurance / Handling Precautions |
| 中文描述： | 質(zhì)量與可靠性保證/操作注意事項 |
| 文件頁數(shù)： | 37/48頁 |
| 文件大?。?/td> | 390K |
| 代理商： | TMP93C071F |
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Quality and Reliability Assurance / Handling Precautions
030901
QUA-37
2002-02-20
4.3.7 Load Capacitance
Some devices display increased delay times if the load capacitance is large. Also,
large charging and discharging currents will flow in the device, causing noise.
Furthermore, since outputs are shorted for a relatively long time, wiring can
become fused.
Consult the technical information for the device being used to determine the
recommended load capacitance.
4.3.8 Thermal Design
The failure rate of semiconductor devices is greatly increased as operating
temperatures increase. As shown in Figure 4.2, the internal thermal stress on a
device is the sum of the ambient temperature and the temperature rise due to
power dissipation in the device. Therefore, to achieve optimum reliability, observe
the following precautions concerning thermal design:
(1)
(2)
Keep the ambient temperature (Ta) as low as possible.
If the device’s dynamic power dissipation is relatively large, select the
most appropriate circuit board material, and consider the use of heat
sinks or of forced air cooling. Such measures will help lower the thermal
resistance of the package.
Derate the device’s absolute maximum ratings to minimize thermal stress
from power dissipation.
θ
ja =
θ
jc +
θ
ca
θ
ja = (Tj – Ta)/P
θ
jc = (Tj – Tc)/P
θ
ca = (Tc – Ta)/P
in which
θ
ja = thermal resistance between junction and surrounding air (°C/W)
θ
jc = thermal resistance between junction and package surface, or
internal thermal resistance (°C/W)
θ
ca= thermal resistance between package surface and
surrounding air, or external thermal resistance (°C/W)
Tj = junction temperature or chip temperature (°C)
Tc = package surface temperature or case temperature (°C)
Ta = ambient temperature (°C)
P
= power dissipation (W)
(3)
Tc
θ
ca
Ta
Tj
θ
jc
Figure 4.2 Thermal Resistance of Package
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