參數(shù)資料
型號(hào)： TLV977-10CPFB
廠商： TEXAS INSTRUMENTS INC
元件分類： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PQFP48
封裝： PLASTIC, TQFP-48
文件頁(yè)數(shù)： 5/21頁(yè)
文件大小： 289K
代理商： TLV977-10CPFB
TLV977-10
3-V, 10-BIT, 21 MSPS, AREA CCD SENSOR PROCESSOR
SLAS229 – AUGUST 1999
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
CDS/PGA signal processor
The output from the CCD sensor is first fed to a correlated double sampler (CDS). The CCD signal is sampled
and held during the reset reference interval and the video signal interval. By subtracting two resulting voltage
levels, the CDS removes low frequency noise from the output of the CCD sensor and obtains the voltage
difference between the CCD reference level and the video level of each pixel. Two sample/hold control pulses
(SR and SV) are required to perform the CDS function.
The CCD output is capacitively coupled to the TLV977–10. The ac coupling capacitor is clamped to establish
proper dc bias during the dummy pixel interval by the CLAMP input. The bias at the input to the TLV977-10 is
set to 1.2 V. Normally, the CLAMP is applied at the sensor’s line rate. Connect a capacitor with a value ten times
larger than the input ac coupling capacitor between the CLREF terminal and the AGND.
When operating the TLV977-10 at its maximum speed, the CCD internal source resistance should be less than
50
. Otherwise, the CCD output buffering is required.
The signal is sent to the PGA after the CDS function is complete. The PGA gain is adjustable from 0 to 36 dB
by programming the internal gain register via the serial port. The PGA is digitally controlled with 9-bit resolution
on a linear dB scale, resulting in a 0.09 dB gain step. The gain can be expressed by the following equation,
Gain = PGA code
× 0.09375 dB
Where: PGA code has a range of 0 to 383,
For example, If PGA code = 64, then the PGA Gain = 6 db (or gain of 2)
The TLV977-10 has direct access to the PGA outputs through the TPP terminal and the TPM terminal. See
Test
Register Description for details.
ADC
The ADC employs a pipelined architecture to achieve high throughput and low power consumption. Fully
differential implementation and digital error correction ensure 10-bit resolution.
The latency of the ADC data output is 4.5 ADCCLK cycles as shown in Figure 1. Pulling OE (terminal 24) high
puts the ADC output in high impedance.
user DACs
The TLV977-10 includes two user DACs that can be used for external analog settings. The output voltage of
each DAC can be independently set and has a range of 0 V to the supply voltage with 8-bit resolution. When
the user DACs are not in use in a camera system, they can be put in the standby mode by programming control
bits in the control register.
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