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參數(shù)資料
| 型號： | TLV977-10CPFB |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, TQFP-48 |
| 文件頁數(shù)： | 20/21頁 |
| 文件大?。?/td> | 289K |
| 代理商： | TLV977-10CPFB |
TLV977-10
3-V, 10-BIT, 21 MSPS, AREA CCD SENSOR PROCESSOR
SLAS229 – AUGUST 1999
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
BLKG
TPP
TPM
AVDD4
AGND4
OBCLP
STBY
RESET
CS
SDIN
SCLK
ADCCLK
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
DIN
PIN
AVDD2
AGND2
DGND
DVDD
D0
D1
D2
D3
D4
D5
TLV977CPFB
1
F
SR Input
SV Input
CLAMP Input
0.1
F
AVDD
0.1
F
AVDD
0.1
F
1
F
0.1
F
1
F
1
F
1
F
BLKG Input
TPP Output
TPM Output
OBCLP Input
STBY Input
RESET Input
CS Input
SDIN Input
SCLK Input
ADCCLK Input
0.1
F
AVDD
DACT Output
DAC02 Output
DAC01 Output
OE Input
0.1
F
AVDD
0.1
F
DIVDD
D (0–9)
0.1
F
AVDD
0.1
F
DVDD
0.1
F
AREA
CCD
Analog Ground
Digital Ground
AVDD
3 V
DVDD
3 V
DIVDD
1.8 V to 4.4 V
48
47
46
45
44
43
42
41
40
39
38
37
13
14
15
16
17
18
19
20
21
22
23
24
CLREF
CLAMP
SV
SR
AGND1
AV
SS
RPD
RMD
RBD
AGND5
DD1
V
AV
DD5
AV
DD3
DI
VDD
D6
D7
D8
D9
DIGND
AGND3
DAC01
DAC02
DACT
OE
(See Note D)
NOTES: A. All analog outputs should be buffered if the load is resistive If the load is capacitive with more than 2 pF loading.
B. When using the TPP and TPM pins to test internal PGA, the AVDD supply voltage should be 3.3 V.
C. Clock signals on the TPP and TPM terminals are inverted.
D. Place these two capacitors as close to the device as possible.
Figure 3. Typical Application Connection
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