參數(shù)資料
型號(hào)： TLV320ALC23
廠商： Texas Instruments, Inc.
元件分類： Codec
英文描述： Evaluation Platform for the TLV320ALC23 Stereo Audio CODEC and TLV230DAC23 Stereo DAC
中文描述： 評(píng)估平臺(tái)為TLV320ALC23 DAC的立體聲音頻編解碼器和立體聲TLV230DAC23
文件頁(yè)數(shù)： 8/46頁(yè)
文件大?。?/td> 452K
代理商： TLV320ALC23
SLAS428 AUGUST 2004
www.ti.com
8
AUDIO INTERFACE TIMING DIAGRAMS
LRCK/ADWS
BCLK
DIN
td(WS)
ts(DI)
th(DI)
Figure 1. I
2
S/LJF/RJF Timing in Master Mode
TYPICAL TIMING REQUIREMENTS (FIGURE 1)
All specifications at 25
°
C, DVDD = 1.8 V (1)
PARAMETER
IOVDD = 1.1 V
MIN
IOVDD = 3.3 V
MIN
UNITS
MAX
25
MAX
15
td(WS)
ts(DI)
th(DI)
tr
tf
(1)These parameters are based on characterization and are not tested in production.
LRCK delay time
ns
DIN setup time
6
6
ns
DIN hold time
6
6
ns
Rise time
10
6
ns
Fall time
10
6
ns
LRCK/ADWS
BCLK
DIN
td(WS)
ts(DI)
th(DI)
td(WS)
Figure 2. DSP Timing in Master Mode
TYPICAL TIMING REQUIREMENTS (FIGURE 2)
All specifications at 25
°
C, DVDD = 1.8 V(1)
PARAMETER
IOVDD = 1.1 V
MIN
IOVDD = 3.3 V
MIN
UNITS
MAX
MAX
td(WS)
ts(DI)
th(DI)
tr
tf
(1)These parameters are based on characterization and are not tested in production.
LRCK delay time
25
15
ns
DIN setup time
6
6
ns
DIN hold time
6
6
ns
Rise time
10
6
ns
Fall time
10
6
ns
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